Experimental analysis of the symmetry of approximate adder designs in FPGA and ASIC

• Tiago Almeida UFT / UNICAMP
• Isaías Felzmann UNICAMP
• Lucas Wanner UNICAMP

Resumo

The approximate hardware design is a suitable candidate for newer custom designs to improve performance, resource usage, and energy efficiency. Many researchers have used different approaches to creating simulated experiments, such as FPGA and ASIC. This fact can imply deviation in the independent variable under observation, i.e., the area utilization, and power dissipation, which can vary asymmetrically. However, how asymmetrical is this variation? What if we used a high-level synthesis approach? Can a characterization of the ASIC design be transferred to an FPGA design? Thus, this research has analyzed power dissipation, and resource utilization (LUT+FF) in approximate adders to characterize the resource usage of design accelerators in FPGA and ASIC from the EvoApprox library. The application to be tested was the Sobel filter for image processing. We used Polarfire, Arty 35T, and Alveo U250 FPGAs. The hypotheses of the experiment were evaluated using three different statistical tests, One-Way ANOVA, Tukey’s test, and Bartlett’s test. We found that even though ASICs and FPGAs are commonly considered with different resource usage, approximated designs in ASIC can be statistically similar to FPGAs depending on the application, and the difference between them could be negligible for power and mostly for the area.

Palavras-chave: Approximate Adders, ASIC, FPGA, Sobel Filter