Automated Generation of HDL Implementations of Dadda and Wallace Tree Multipliers

• Lucas G. de Castro USP
• Henrique S. Ogawa USP
• Bruno de C. Albertini USP

Resumo

Convolutional Neural Networks are being studied to provide features such as real time image recognition. One of the key operations to support HW implementations of this type of network is the multiplication. Despite the high number of operations required by Convolutional Neural Networks, they became feasible in the past years due the high availability of computing power, present on devices such as Graphic Processing Units. However, those implementations are unsuitable for energy constrained scenarios, such as embedded devices. FPGAs are programmable devices that are being considered as a low power alternative for GPUs. This work proposes and implement a generator of two fast combinatorial multipliers: Dadda and Wallace tree. Our generator is capable of generating structural descriptions of both designs for any operand width, an operation considered unfeasible by hand. We evaluated our generator using two low-cost FPGA platforms, easily found on the market.

Palavras-chave: Field programmable gate arrays, Hardware design languages, Delays, Complexity theory, Hardware, Logic gates, Graphics processing units