Design Space Exploration Using UTNoCs and Genetic Algorithm
Resumo
During the design of multiprocessor architectures, the design space exploration step may be aided by tools that assist and accelerate this process. The project of architectures whose communications are based on Networks-on-Chip (NoCs), usually relies on regular topologies. Following another path, this work presents a high-level design space exploration tool aiming at generate optimized irregular NoC topologies. The solutions generated by the tool are called UTNoC, Undefined Topology Network-on-Chip. Taking as entry, communications behaviour modelled as traffic patterns and a set of communication routers, the tool searches for optimized ways to connect them, in order to improve performance and to reduce the total number of connections. The tool is based on evolutionary algorithms. Simulation results show improvements in reducing both the average latency and the number of connections, when compared to an equivalent Mesh topology.
