NeuroHLS: A Flexible Framework for Accelerating SNNs on FPGAs

• Renan Carlos Gomes de Farias UFSM
• Fernando Pedrazzi Pozzer UFSM
• Mateus Beck Rutzig UFSM

Resumo

Field-Programmable Gate Arrays (FPGAs) have emerged as a promising platform for accelerating AI applications in IoT devices. In this context, Spiking Neural Networks (SNNs) have demonstrated superior energy efficiency compared to traditional artificial neural networks when implemented on FPGAs. Although various frameworks have been proposed for mapping SNNs onto FPGAs, none of them have leveraged High-Level Synthesis (HLS), which facilitates faster development cycles and greater design transparency. This work introduces NeuroHLS, an HLS-based framework for implementing SNNs on FPGAs. NeuroHLS offers both resource- and latency-optimized implementation strategies, and supports fine-grained parameter customization at the layer level. To validate the framework, a 784128-10 SNN was implemented and evaluated on the N-MNIST dataset. Performance was benchmarked against existing state-of-the-art frameworks. Experimental results demonstrate that both implementation strategies offered by NeuroHLS significantly outperform existing approaches in terms of inference latency and energy efficiency. In particular, one configuration achieved an inference latency of 0.8us and an average energy consumption of 2.16uJ per inference.

Palavras-chave: Energy consumption, Codes, Computational modeling, Spiking neural networks, C languages, Benchmark testing, Energy efficiency, Internet of Things, Hardware design languages, Field programmable gate arrays, Spiking Neural Networks, High-Level Synthesis, Framework, FPGA