TORVS: A Lightweight Dual-Issue Superscalar RISC-V Core for FPGA-Based Systems

• Lucas Arruk Mendes UFSCar
• Maurício Figueiredo UFSCar
• Ricardo Menotti UFSCar

Resumo

TORVS is a lightweight, open-source, parameterizable, dual-issue, in-order superscalar RISC-V core optimized for FPGA-based systems. It implements the RV32I instruction set and comprises two five-stage symmetric pipelines: fetch, decode, execute, memory access, and write-back. Parameterization is achieved through two orthogonal tuning axes: (i) branch predictor selection and (ii) the subset of instructions allowed for dispatch to the second pipeline. Each combination of parameters defines a unique design point with its own area–performance trade-off, characterized by FPGA usage, cycles per instruction (CPI), and maximum operating frequency. All configurations were validated with two standard benchmarks: CoreMark (1.176–1.600 CoreMark/MHz) and Dhrystones (1.708–2.331 DMIPS/MHz). The core was synthesized and successfully tested on an Intel DE10-Standard FPGA board. Several comparisons with a variety of processors were made to understand the advantages and disadvantages of a lightweight core. The conclusion shows that the lightweight design of TORVS delivers competitive performance in basic operations, whereas its efficiency declines for more complex workloads.

Palavras-chave: Out of order, Pipelines, Benchmark testing, Systems engineering and theory, Prediction algorithms, Complexity theory, Field programmable gate arrays, Tuning, Stress, Standards, lightweight, superscalar, in-order, parameter-ized, open-source, RISC-V, FPGA