A Lightweight RISC-V Vector Merge Instruction to Boost SpMxDV Algorithm

• Manuel Osterno PUCRS
• César Marcon PUCRS
• Jarbas Silveira UFC
• Jardel Silveira UFC

Abstract

Sparse linear algebra plays a crucial role across various fields because it reduces computational workload and optimizes memory usage. However, the irregular structure of sparse data creates difficulties for traditional software and hardware systems. Although dedicated accelerators can boost performance, they often lack the flexibility of general-purpose processors and depend on processor communication, which can introduce bottlenecks. This work tackles these challenges by proposing a tiling method that enhances the use of vector registers and by extending the RISC-V Vector (RVV) instruction set with a custom merge instruction. The project experimented with gem5 demonstrates that the tiled vector version delivered average performance gains of up to 1.31× and 1.67× for 95% and 65% sparsity, respectively, and the version incorporating the proposed merge instruction achieved speedups of up to 1.80× and 5.31× compared to a standard baseline. Additionally, the conversions required to implement the instructions did not exceed 2.5% of the area overhead for the SIMD Unit of the Sargantana processor.

Keywords: Single instruction multiple data, Instruction sets, Machine learning, Performance gain, Systems engineering and theory, Vectors, Software, Registers, Sparse matrices, Standards, Vector ISA, Sparsity, RISC-V, Acceleration