A Simulation Methodology for Transparent Coarse-Grained Reconfigurable Architectures

• Thiago R. B. Da S. Soares IFPI
• Ivan Saraiva Silva UFPI

Resumo

Coarse-Grained Reconfigurable Architectures (CGRAs) are flexible accelerators that exploit instruction-level parallelism with low reconfiguration overhead. Transparent CGRAs extend this model by dynamically generating configurations at runtime, eliminating the need for compiler toolchains and improving adaptability. However, designing transparent CGRAs is a complex task that requires tight integration with the host processor, including access to pipeline stages and specialized mechanisms for synchronization. These requirements often result in highly customized, non-portable implementations that hinder reproducibility and design exploration. Moreover, existing CGRA simulation tools are poorly suited for transparent models, as they rely on static configuration generation and code annotations. To address this gap, we present a simulation methodology specifically tailored for transparent CGRAs. The proposed system models runtime profiling, mapping, and execution using a modular architecture. It supports customizable topologies, speculation levels, mapping algorithms, and processing element capabilities. To demonstrate its capabilities, we simulated eight transparent CGRA models under a unified setup and analyzed the impact of topology, available operations, memory integration, and speculation on system performance. The results demonstrate the framework’s effectiveness for performance evaluation and design space exploration in transparent CGRAs. Additionally, we analyzed the memory system and its impact on performance, area, and energy consumption.

Palavras-chave: Performance evaluation, Runtime, System performance, Pipelines, Parallel processing, Reproducibility of results, Topology, Reconfigurable architectures, Space exploration, Synchronization, CGRA, Transparent CGRA, Mapping algorithms, Simulation framework