Electromigration Aware Cell Design

  • Gracieli Posser UFRGS
  • Ricardo Reis UFRGS
  • Sachin S. Sapatnekar University of Minnesota

Resumo


Electromigration (EM) in on-chip metal interconnects is a critical reliability failure mechanism in nanometer-scale technologies. This work addresses the problem of EM on signal interconnects and on Vdd and Vss rails within a standard cell. An approach for modeling and efficient characterization of cell-internal EM is developed, incorporating Joule heating effects. We also present a graph-based algorithm that computes the currents when the pin position is moved avoiding a new characterization for each pin position and consequently reducing considerable the characterization time. We use the cell lifetime analysis to determine the lifetime of large benchmark circuits, and show that these circuit lifetimes can be improved up to 80.95% by avoiding the critical output, Vdd, and Vss pin positions of the cells, using minor layout modifications.

Referências

NanGate 45nm Open Cell Library. http://www.nangate.com.

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Lee, K.-D. (2012). Electromigration recovery and short lead effect under bipolar- and unipolar-pulse current. In Proceedings of the IEEE International Reliability Physics Symposium, pages 6.B.3.1–6.B.3.4.

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Posser, G., de Paris, L., Mishra, V., Jain, P., Reis, R., and Sapatnekar, S. S. (2015a). Reducing the signal electromigration effects on different logic gates by cell layout optimization. In 2015 IEEE 6th Latin American Symposium on Circuits Systems (LASCAS), pages 1–4.

Posser, G., Mishra, V., Jain, P., Reis, R., and Sapatnekar, S. S. (2014a). A systematic approach for analyzing and optimizing cell-internal signal electromigration. In Proceedings of the International Conference on Computer-Aided Design, ICCAD ’14.

Posser, G., Mishra, V., Jain, P., Reis, R., and Sapatnekar, S. S. (2015b). Analyzing and optimizing cell-internal signal electromigration. In South Symposium on Microelectronics, SIM 2015, Santa Maria, RS.

Posser, G., Mishra, V., Jain, P., Reis, R., and Sapatnekar, S. S. (2015c). Impact on performance, power, area and wirelength using electromigration-aware cells. In IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Posser, G., Mishra, V., Jain, P., Reis, R., and Sapatnekar, S. S. (2016). Cell-internal electromigration: Analysis and pin placement based optimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 35(2):220–231.

Posser, G., Mishra, V., Reis, R., and Sapatnekar, S. S. (2014b). Analyzing the electromigration effects on different metal layers and different wire lengths. In IEEE International Conference on Electronics, Circuits and Systems (ICECS), pages 682–685.

Sapatnekar, S. S., Mishra, V., Jain, P., Posser, G., and Reis, R. (2015). Cell-level signal electromigration. US Patent Application number 20150347665.

Wang, C.-H., Tam, K.-H., and Chen, H.-Y. (2014). Automatic place and route method for electromigration tolerant power distribution. US Patent 8,694,945.
Publicado
04/07/2016
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POSSER, Gracieli; REIS, Ricardo; SAPATNEKAR, Sachin S.. Electromigration Aware Cell Design. In: CONCURSO DE TESES E DISSERTAÇÕES (CTD), 29. , 2016, Porto Alegre. Anais [...]. Porto Alegre: Sociedade Brasileira de Computação, 2016 . p. 85-90. ISSN 2763-8820. DOI: https://doi.org/10.5753/ctd.2016.9144.