Biased Mutation and Tournament Selection Approaches for Designing Combinational Logic Circuits via Cartesian Genetic Programming
Cartesian Genetic Programming (CGP) is often applied to design combinational logic circuits. However, there is no consensus in the literature regarding the more appropriate objective function when it is desired to minimize the number of logic gates of the circuit. Thus, we analyze here two strategies: the minimization of the number of logic gates and the maximization of the number of wire gates. Additionally, a biased mutation strategy for CGP, which were previously presented and tested only to find a feasible solution, are extended in this paper for the subsequent optimization step. Several configurations were proposed and tested varying objective function and selection schemes. Compu- tational experiments are conducted with some benchmark circuits to relatively compare the proposed methods, and the results obtained are better than those found by the other techniques considered here.
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