Performance Optimization of Persistent Memory Systems Through Phase-Based Transactional Memory
Abstract
The emerging persistent memory technologies (PM) are aimed to eliminate the gap between main memory and storage. Nevertheless, its adoption requires measures to guarantee consistency, since crash failures might render the program in an unrecoverable state. In this context, the usage of durable transactions is one of the main investigated approaches to ease the adoption of PM. However, today's implementations are based exclusively on software (SW) or hardware (HW), which might degrade system performance. This paper presents NV-PhTM, a transactional system for PM that delivers the best out of both HW and SW transactions by dynamically changing the execution according to the application's characteristics.
Keywords:
Computer and processor architectures, Language, compilers, and tools for Parallel and Distributed Computing
References
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Carvalho, J. P. D., Araujo, G., and Baldassin, A. (2018). The case for phase-based transactional memory. IEEE Transactions on Parallel and Distributed Systems.
Castro, D., Romano, P., and Barreto, J. (2018). Hardware transactional memory meets memory persistency. In 2018 IEEE International Parallel and Distributed Processing Symposium (IPDPS), pages 368–377, Vancouver, BC, Canada. IEEE.
Harris, T., Larus, J., and Rajwar, R. (2010). Transactional Memory. Morgan and Claypool Publishers, 2nd edition.
Minh, C. C., Chung, J., Kozyrakis, C., and Olukotun, K. (2008). Stamp: Stanford trans- actional applications for multi-processing. In 2008 IEEE International Symposium on Workload Characterization, pages 35–46, Seattle, WA, USA. IEEE.
Mutlu, O. and Subramanian, L. (2014). Research problems and opportunities in memory systems. Supercomputing Frontiers and Innovations: an International Journal, 1(3):19–55.
Carvalho, J. P. D., Araujo, G., and Baldassin, A. (2018). The case for phase-based transactional memory. IEEE Transactions on Parallel and Distributed Systems.
Castro, D., Romano, P., and Barreto, J. (2018). Hardware transactional memory meets memory persistency. In 2018 IEEE International Parallel and Distributed Processing Symposium (IPDPS), pages 368–377, Vancouver, BC, Canada. IEEE.
Harris, T., Larus, J., and Rajwar, R. (2010). Transactional Memory. Morgan and Claypool Publishers, 2nd edition.
Minh, C. C., Chung, J., Kozyrakis, C., and Olukotun, K. (2008). Stamp: Stanford trans- actional applications for multi-processing. In 2008 IEEE International Symposium on Workload Characterization, pages 35–46, Seattle, WA, USA. IEEE.
Mutlu, O. and Subramanian, L. (2014). Research problems and opportunities in memory systems. Supercomputing Frontiers and Innovations: an International Journal, 1(3):19–55.
Published
2019-04-12
How to Cite
MURARI, Rafael; CARVALHO, João Paulo; ARAUJO, Guido ; BALDASSIN, Alexandro .
Performance Optimization of Persistent Memory Systems Through Phase-Based Transactional Memory . In: REGIONAL SCHOOL OF HIGH PERFORMANCE COMPUTING FROM SÃO PAULO (ERAD-SP), 10. , 2019, Campinas.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
2019
.
p. 29-32.
DOI: https://doi.org/10.5753/eradsp.2019.13590.
