Applications’ error sensitivity at RISC-V architecture

• João Fabrício Filho UTFPR / UNICAMP http://orcid.org/0000-0001-6036-4031
• Isaias B. Felzmann UNICAMP https://orcid.org/0000-0003-3048-8310
• Lucas F. Wanner UNICAMP https://orcid.org/0000-0002-5564-698X

DOI: https://doi.org/10.5753/eradsp.2020.16886

Abstract

Architectures that implement the RISC-V instruction set are appropriate to the context of embedded systems. The demand for lower energy consumption and higher performance in this context is growing, and the approximation of memory elements has the potential to achieve both benefits. Nevertheless, the sensitivity to errors of applications may prevent higher benefits because of execution crashes or lower quality results. In this work, we propose the evaluation of the applications’ sensitivity to errors in data stored into approximate memories running under the RISC-V architecture. Our simulations expose all data memory to an error model, making evident the correlation between the growth of execution crashes and the lowering of the quality of the results. Considering a quality requirement of 90%, all 3 evaluated applications tolerate different approximation levels in the logarithm scale, reaching the error rate of 10^-7.

Keywords: Approximate Computing, Approximate Memories, Error Sensitivity, Error Tolerance

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