Revisiting and adding gates to a processor dedicated to hardware-based quantum algorithm simulation

• Pedro J. Silveira UFS
• Breno S. Nascimento UFS
• Calebe M. Conceição UFS
• Rodolfo B. Garcia UFS

DOI: https://doi.org/10.5753/erbase.2025.13732

Abstract

Current approaches to implementing quantum-algorithm simulations in hardware suffer from performance and complexity issues. In this article, we revisit an FPGA implementation of a dedicated 3-qubit processor that supports the S gate, T gate, Hadamard gate, Pauli-X gate, CNOT gate, and Toffoli gate. The proposed architecture combines high performance with design simplicity by enabling the efficient simulation of a quantum circuit’s behavior through a programmable, RISC-inspired model. This eliminates the need to re-synthesize the design, reduces potential errors, and overcomes some of the limitations of existing solutions. Such an approach could represent a viable alternative for the development and validation of new quantum-based systems.

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