NCESPARC+: A Multithreaded SPARC Architecture for the Multiplus Multiprocessor

• J. S. Aude UFRJ
• F. R. S. Martins UFRJ
• M. A. S. Barbosa UFRJ
• M. Joao Jr. UFRJ
• M. T. Young UFRJ
• S. B. Pinto UFRJ

DOI: https://doi.org/10.5753/sbac-pad.1999.19769

Resumo

NCESPARC+ is a SPARC V.8 architecture with hardware support to a variable number of thread contexts, which is under development for use within the framework of the Multiplus distributed shared-memory multiprocessor. It is expected to provide an efficient and automatic mechanism to hide the latency of busy-waiting synchronization loops, cache-coherence protocol and remote memory access operations within the Multiplus multiprocessor. NCESPARC+ performs context-switching in at most four processor cycles whenever there is an instruction cache miss, a data dependence in relation to the destination operand of a pending load instruction or a busy-waiting synchronization loop. Results of simulation experiments show the impact of some architectural parameters on the NCESPARC+ processor performance and demonstrate that the use of multiple thread contexts can effectively produce a much better utilization of the processor when long latency operations are performed.

Palavras-chave: Multithreaded Architectures, SPARC Architecture, Context-Switching, Latency Hiding

Referências

AGARWAL, A., et al. The MIT Alewife Machine: Architecture and Performance. Proc. of the IEEE. March 1999, pp. 430-444

AUDE, J.S., et al. The Multiplus/Mulplix Parallel Processing Environment. Proc. of the Intern'l Symp. on Parallel Architectures, Algorithms and Networks, Beijing, China, June 1996, pp. 50-56

BYRD, G.T., HOLLIDAY, M.A. Multithreaded Processor Architectures. IEEE Spectrum, Aug. 1995, pp. 38-46

TULLSEN, D.M., EGGERS, S.J., LEVY, H.M. Simultaneous Multithreading: Maximizing On-Chip Parallelism. Proc. 22nd Int'1 Symp. on Computer Architecture, Santa Margherita Ligure, ltaly, 1995

WEAVER, D.L., GERMOND, T. The SPARC Architecture Manual - Version 8. Prentice-Hall, 1992