A Vector Orthogonal Multiprocessor NEOMP and its Use in Neural Network Mapping

Jose Hiroki Saito

doi:10.5753/sbac-pad.1999.19800

Jose Hiroki Saito UFSCar

DOI: https://doi.org/10.5753/sbac-pad.1999.19800

Resumo

A vector Orthogonal Multiprocessor architecture NEOMP and its use by a feedforward artificial neural network, Neocognitron, is described. The proposed architecture is composed by several vector processing units, and a scalar control processor, which access the memory modules in a orthogonal fashion. The performance analysis of the architecture is realized, identifying the concurrent computation grains in the neocognitron, which are attributed to the vector processors. The analysis of the architecture showed that its speed-up is linear in a wide range, where the implementation of NEOMP is appropriate. The scalar control processor and the vector processing unit hardware prototype were simulated and showed the feasibility of their implementation, each one in a single FPGA, which inspire the construction of NEOMP as a real time neocognitron, and other feedforward neural network systems, using vector orthogonal multiprocessor architecture.

Palavras-chave: orthogonal multiprocessor, OMP, vector processor, parallel processing, neocognitron, neural network, NEOMP

Referências

AMAWY, A.El & LULASINGHE, P. Algorithmic Mapping of Feedforward Neural Networks onto Multiple Bus Systems, IEEE Trans. On Parallel and Distributed Systems Vol. 8, N.2, pp. 130-136, Feb. 1997.

FUKUSHIMA, K., Neural-network model for a mechanism of pattern recognition unaffected by shift in position neocognitron, Trans. IEICE Japan, vol. 62-A, no. 10, pp. 658-665, 1979.

FUKUSHIMA, K.& MIYAKE, S., Neocognitron: A New Algorithm for Pattern Recognition Tolerant of Deformations and Shift in Position, 278 SBAC-PAD'99 11th Symposium on Computer Architecture and High Performance Computing-Natal-Brazil Pattern Recognition, vol. 15, no.6, pp.455-469, 1982.

FUKUSHIMA,.K. & WAKE, N., Improved Neocognitron with Bend-Detecting Cells, IEEE - International Joint Conference on Neural Networks, Baltimore, Maryland, June 7-11, 1992, pp. 190-195, 1992.

FUKUSHIMA,K.& TANIGAWA, M., Use of Different Thresholds in Learning and Recognition, Neurocomputing, 11, pp. 1-17, 1996.

HERZEN,B.V., Signal Processing at 250 MHz Using High-Performance FPGA's, IEEE Trans. On VLSI Systems, Vol. 6, N.2, pp. 238-246, Jun. 1998.

HWANG, K.; TSENG, P & KIM, D. , An Orthogonal Multiprocessor for Parallel Scientific Computations, IEEE Trans. On Computers, Vol.38,N.1,pp.47-61, Jan. 1989

HWANG,K.- Advanced Computer Architecture-Parallelism, Scalability, Programmability. McGrawHill, Sing., 1993.

IWATA, A.& AMEMIYA, Y.- Neural Network LSI. The Institute of Electronics, Information and Communication Engineers, Japan, 1995.

KUMAR, V.; SHEKHAR, S.& AMIN, M.B., A Scalable Parallel Formulation of the Backpropagation Algorithm for Hypercubes and Related Architectures, IEEE Trans. On Parallel and Distributed Systems, Vol. 5, N. 10, pp. 1073-1090, Oct. 1994.

LEWIS, D.M., GALLOWAY, D.R., IERSSEL, M., ROSE, J. & CHOW, P., The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System, IEEE Trans. On VLSI Systems, Vol. 6,N.2,pp. 188-198, Jun. 1998.

SAITO, J.H. & FUKUSHIMA, K. , Modular Structure of Neocognitron to Pattem Recognition, Proc. ICONIP'98, Fifth Int. Conf. On Neural Information Processing, Kitakyushu, Japan, pp.279-282, Oct. 1998.

TSUTSUI, A. & MIYASAKI, T., ANTon - Yards: FPGA/MPU Hybrid Architecture for Telecommunication Data Processing. IEEE Trans. On VLSI Systems, Vol. 6, N.2, pp. 199-211, Jun. 1998.

Y AO, X., Following the Path of Evolvable Hardware, Communications of the ACM, Vol. 42, N.4, Ap. 1999.

YASUNAGA, M., HACHIYA, I.; MOKI, K. & KIM, J., Fault Tolerant Self-Organizing Map Implemented by Wafer Scale Integration, IEEE Trans. On VLSI Systems, Vol. 6, N.2, Jun. 1998.