Avaliação de Modelos de Acesso à Memória de Dados em Arquiteturas Super Escalares

• Emmanuel M. Pereira UFRJ
• Eliseu M. Chaves Filho UFRJ

DOI: https://doi.org/10.5753/sbac-pad.1999.19804

Resumo

The execution of data memory access instructions is an important issue for processor performance, due to the high frequency of such instructions. This work focus on the execution of memory access instructions in superscalar architectures. Several different memory access models are evaluated, ranging from a simple mechanism in which memory access instructions are executed sequentially in order, to a mechanism which executes memory access instructions in pipeline, out of order and speculatively.

Palavras-chave: ILP, Superscalar Architectures

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