Avaliação de Modelos de Acesso à Memória de Dados em Arquiteturas Super Escalares

  • Emmanuel M. Pereira UFRJ
  • Eliseu M. Chaves Filho UFRJ

Resumo


The execution of data memory access instructions is an important issue for processor performance, due to the high frequency of such instructions. This work focus on the execution of memory access instructions in superscalar architectures. Several different memory access models are evaluated, ranging from a simple mechanism in which memory access instructions are executed sequentially in order, to a mechanism which executes memory access instructions in pipeline, out of order and speculatively.

Palavras-chave: ILP, Superscalar Architectures

Referências

Patterson, D., Hennessy, J., Computer Architecture: A Quantitative Approach, 2nd. Ed., Morgan-Kaufmann, San Francisco, CA, 1997.

Diep, T. A.. Shen, J. P., Performance Evaluation of the PowerPC 620 Microarchitecture, Proceedings of the 22nd International Symposium on Computer Architecture, 1995, pp. 163-175.

Franklin, M., Sohi, G. S., ARB: A Hardware Mechanism for Dynamic Memory Disambiguation, IEEE Transactions on Computers, Vol. 45, No. 5, May 1996. pp. 552-571.

Sun Microsystems, The SPARC Architecture Manual, Version 7, Mountain View, CA. 1987.

Systems Performance Evaluation Corporation, SPEC95 User Manual. 1995.
Publicado
29/09/1999
PEREIRA, Emmanuel M.; CHAVES FILHO, Eliseu M.. Avaliação de Modelos de Acesso à Memória de Dados em Arquiteturas Super Escalares. In: INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING (SBAC-PAD), 11. , 1999, Natal. Anais [...]. Porto Alegre: Sociedade Brasileira de Computação, 1999 . p. 299-304. DOI: https://doi.org/10.5753/sbac-pad.1999.19804.