Performance Evaluation with Petri Nets of a Bus-based Multithreaded Multiprocessor

• Marcelo H. Cintra USP
• Wilson V. Ruggiero USP

DOI: https://doi.org/10.5753/sbac-pad.1996.19812

Resumo

Multithreaded architectures have been actively investigated in recent years to build large-scale multiprocessors that are more tolerant to intra-context instruction dependencies and large synchronization and memory access latencies. In this paper we develop a multilevel Petri net model of a bus-based multiprocessor system and use this model to verify the impact of multithreading in processor utilization and network latency. Using a multilevel modeling methodology for Petri nets we show that multithreaded architectures have higher processor utilizations, but offer a higher load to the interconnection network and the memory system.

Referências

Agarwal, A., Lim, B. H., Kranz, D., and Kubiatowicz, J., APRIL: A Processor Architecture for Multiprocessing, In Proceedings of the 17th Annual International Symposium on Computer Architecture, pp. 104-114, May 1990

Agarwal, A., Performance Tradeoffs in Multithreaded Processors, IEEE Transactions of Parallel and Distributed Systems, vol. 3, no. 5, September 1992

Agerwala, T., Putting Petri Nets to Work, Computer, pp. 85-94, December 1979

Alverson, R., Callahan, D., Cummings, D., Koblenz, B., Porterfield, A., and Smith, B., The Tera Computer System, In Proceedings of the ACM ICS, pp. 1-6, June 1990

Cintra, M. H. and Ruggiero, W. V., A Tool for Modeling and Simulation of Computer Architectures Using Petri Nets, In Proceedings of the VII Brazilian Symposium on Computer Architecture, August 1995

Culler, D. E., Sah, A., Schauser, K. E., von Eicken T., Wawrzynek, J., Fine-grain Parallelism with Minimal Hardware Support: A Compiler-Controlled Threaded Abstract Machine, In Proceedings of the Fourth lnternational Conference on Architectural Support for Programming Languages and Operating Systems, April1991

Halstead, R. H. Jr. and Fujita, T., MASA: A Multithreaded Processor Architecture for Parallel Symbolic Computing, In Proceedings of the 15th Annual lnternational Symposium on Computer Architecture, pp. 443-451, May 1988

Jain, R:, The Art of Computer Systems Performance Analysis: Techniques for Experimental Design, Measurement, Simulation, and Modeling, John Wiley, 1992

Laudon, M., Gupta, A., and Horowitz, M., Interleaving: A Multithreading Technique Targeting Multiprocessors and Workstations, In Proceedings of the 6th International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 308-318, October 1994

Nemawarkar, S. S., Govindarajan, R., Gao, G. R., Agarwal, V. K., Performance Evaluation of Latency Tolerant Architectures, In Proceedings of the 4th lnternational Conference on Computing and lnformation, pp. 183-186, May 1992

Peterson, J. L., Petri Net Theory and the Modeling of Systems, Prentice-Hall, 1981

Smith, B. J., A Pipelined Shared Resource MIMD Computer, In Proceedings of the 1978 lnternational Conference on Parallel Processing, pp. 6-8, August 1978

Tullsen, D. M., Eggers, S. J., and Levy, H. M., Simultaneous Multithreading: Maximizing On-Chip Parallelism, In Proceedings of the 16th Annual lnternational Symposium on Computer Architecture, pp. 392-403, June 1995

Weber W. D., and Gupta, A., Exploring the Benefits of Multiple Hardware Contexts in a Multiprocessor Architecture: Preliminary Results, In Proceedings of the 16th Annual lnternational Symposium on Computer Architecture, pp. 273-280, June 1989.