Communication and Performance Trade-offs in a Systolic Machine
Resumo
This paper presents the trade-offs concerning lnput-Output communications at the interface of a SIMD systolic machine, and inside the machine. These problems have been raised by the accelerating board we are currently designing. We discuss about the issues involved by VLSI design: cascadability, scalability, fault tolerance, and feasibility. We present the main features of our architecture, and the performances measured with an actual application which proves that despire of the host computer slowness, the I/O bottleneck is not a penalty for the calculation acceleration.
Referências
D. Archambaud, P. Faudemay, "Rapid-2, A Paginated Set-Associative Circuit That Performs Sning Processing", Proceedings of the 1st south american workshop on sning processing, pp 1-13, September 1993
D. Archambaud, P. Faudemay, A. Greiner, "Rapid-2, An Object Oriented Associative Memory Applicable to Genome Data Processing", Proceedings of the 27th annual Hawaii international conference on system sciences, vol 5, pp 100-110, January 1994
R. Barman et al., "Silt: The Bit-Parallel Approach", pp 332-336, IEEE 1990
A. F. W. Coulson et al., "Protein and nucleic acid sequence database searching : a suitable case for parallel processing", Computer Journal, vol 30, n°5, pp 420-424, June 1987
E. Edmiston and R. A. Wagner, "Parallelization of the Dynamic Programming Algorithm for Comparison of Sequences", Proceeding of the International Conference on Parallel Processing, pp 78-80, 1987
F. Herman and C. Sodini, "A Dynamic Associative Processor for Machine Applications", IEEE Micro, June 1992
R. Hughey and D.P. Lopresti, "Architecture of a Programmable Systolic Array", Proceedings of the international conference on systolic arrays, may 1988, pp 41-49
H. T . Kung, "Why Systolic Architectures", Computer, vol 15, pp 37-46, January 1982
D. Lavenier, "An Integrated 2-D Systolic Array for Sning Comparison", Proceedings of the I st south american workshop on sning processing, pp 117-121, September 1993
D. P. Lopresti, "P-NAC: A Systolic Array for Comparing Nucleic Acid Sequences", Computer, vol20, pp98-99, July 1987
A. J. McAuley & C.J. Cotton, "A Self-Testing Reconfigurable CAM", IEEE journal of Solid-State Circuits, vol. 26, W 3, March 1991
M. Motomura et al., "A 1.2-Million Transistor, 33-MHz, 20-b Dictionary Search Processor (DISP) ULSI with a 160-Kb CAM", IEEE journal of Solid-State Circuits, vol. 25, W 5, October 1990
S.B. Needleman & C.D. Wunsch, "A General Method Applicable to the Search for Similarities in the Amíno-Acid Sequence of Two Proteíns", Journal of Molecular Biology, vol48, pp 443-453, 1970
T. Ogura et al., "A 20-Kbit Assocíative Memory LSI for Artificial Intelligence Machínes", IEEE journal of Solid-State Circuits, vol. 24, N° 4, August 1989 XIV Congresso da Sociedade Brasileira de Computação 328
S. P. Popli and M. A. Bayoumi, "A Reconfigurable VLSI Array for Reliability and Yield Enhancement", Proceedings of the intemational conference on systolic arrays, may 1988, pp 631-642
V. K. Prasanna Kumar and Yu-Chen Tsai, "Architecture of a Programmable Systolic Array", Proceedings of the intemational conference on systolic arrays, may 1988, pp 51-60
T. Risset, "Applying Semi-Systolic Techniques to SIMD Programming", Proceedigs of the IFIP 1994, Appl. in Parallel and Distributed Computing, pp 103-112, C. Girault editor
T. F. Smith & M.S. Watennan, "Identification of Common Molecular Subsequences", Journal of Molecular Biology, n° 147, pp 195-197, 1980
Q. F. Stout, "Mesh-Connected Computers with Broadcasting", IEEE trans. on computers, vol C-32, n°9, September 1983
R. A. Wagner & M. J. Fischer, "The String-to-String Correction Problem", Journal of the Association for Computing Machinery, vol. 21, N° 1, pp 168-173, January 1974
P. Wayner, "Smart Memories", Byte, pp 147-152, March 1991
M. Yasunaga et al. , "A Self-Learning Digital Neural Network Using Wafer-Scale LSI", IEEE journal of Solid-State Circuits, vol. 28, N° 2, February 1993
D. Archambaud, P. Faudemay, A. Greiner, "Rapid-2, An Object Oriented Associative Memory Applicable to Genome Data Processing", Proceedings of the 27th annual Hawaii international conference on system sciences, vol 5, pp 100-110, January 1994
R. Barman et al., "Silt: The Bit-Parallel Approach", pp 332-336, IEEE 1990
A. F. W. Coulson et al., "Protein and nucleic acid sequence database searching : a suitable case for parallel processing", Computer Journal, vol 30, n°5, pp 420-424, June 1987
E. Edmiston and R. A. Wagner, "Parallelization of the Dynamic Programming Algorithm for Comparison of Sequences", Proceeding of the International Conference on Parallel Processing, pp 78-80, 1987
F. Herman and C. Sodini, "A Dynamic Associative Processor for Machine Applications", IEEE Micro, June 1992
R. Hughey and D.P. Lopresti, "Architecture of a Programmable Systolic Array", Proceedings of the international conference on systolic arrays, may 1988, pp 41-49
H. T . Kung, "Why Systolic Architectures", Computer, vol 15, pp 37-46, January 1982
D. Lavenier, "An Integrated 2-D Systolic Array for Sning Comparison", Proceedings of the I st south american workshop on sning processing, pp 117-121, September 1993
D. P. Lopresti, "P-NAC: A Systolic Array for Comparing Nucleic Acid Sequences", Computer, vol20, pp98-99, July 1987
A. J. McAuley & C.J. Cotton, "A Self-Testing Reconfigurable CAM", IEEE journal of Solid-State Circuits, vol. 26, W 3, March 1991
M. Motomura et al., "A 1.2-Million Transistor, 33-MHz, 20-b Dictionary Search Processor (DISP) ULSI with a 160-Kb CAM", IEEE journal of Solid-State Circuits, vol. 25, W 5, October 1990
S.B. Needleman & C.D. Wunsch, "A General Method Applicable to the Search for Similarities in the Amíno-Acid Sequence of Two Proteíns", Journal of Molecular Biology, vol48, pp 443-453, 1970
T. Ogura et al., "A 20-Kbit Assocíative Memory LSI for Artificial Intelligence Machínes", IEEE journal of Solid-State Circuits, vol. 24, N° 4, August 1989 XIV Congresso da Sociedade Brasileira de Computação 328
S. P. Popli and M. A. Bayoumi, "A Reconfigurable VLSI Array for Reliability and Yield Enhancement", Proceedings of the intemational conference on systolic arrays, may 1988, pp 631-642
V. K. Prasanna Kumar and Yu-Chen Tsai, "Architecture of a Programmable Systolic Array", Proceedings of the intemational conference on systolic arrays, may 1988, pp 51-60
T. Risset, "Applying Semi-Systolic Techniques to SIMD Programming", Proceedigs of the IFIP 1994, Appl. in Parallel and Distributed Computing, pp 103-112, C. Girault editor
T. F. Smith & M.S. Watennan, "Identification of Common Molecular Subsequences", Journal of Molecular Biology, n° 147, pp 195-197, 1980
Q. F. Stout, "Mesh-Connected Computers with Broadcasting", IEEE trans. on computers, vol C-32, n°9, September 1983
R. A. Wagner & M. J. Fischer, "The String-to-String Correction Problem", Journal of the Association for Computing Machinery, vol. 21, N° 1, pp 168-173, January 1974
P. Wayner, "Smart Memories", Byte, pp 147-152, March 1991
M. Yasunaga et al. , "A Self-Learning Digital Neural Network Using Wafer-Scale LSI", IEEE journal of Solid-State Circuits, vol. 28, N° 2, February 1993
Publicado
01/08/1994
Como Citar
ARCHAMBAUD, Denis; SILVA, Ivan Saraiva; FAUDEMAY, Pascal.
Communication and Performance Trade-offs in a Systolic Machine. In: INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING (SBAC-PAD), 6. , 1994, Caxambu.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
1994
.
p. 317-328.
DOI: https://doi.org/10.5753/sbac-pad.1994.21894.
