A Reconfigurable Computer REOMP
Resumo
This work describes a proposal of reconfigurable computer, and their application to hardware implementations of neural networks. Although the neural network functions correspond to the brain functions, our computer is based on the current technology, which is completely different from the internal structure of the brain based on the neuronal cells. The proposed Reconfigurable Orthogonal Multiprocessor. REOMP, is based on processing units that are reconfigured to execute the algorithms by demanding driven rule. The performance analysis of the architecture is made with the implementation of an artificial neural network, neocognitron, which involves concurrent operations of a great number of artificial neurons. The analysis of the architecture showed that its speed-up is linear in a wide range, where the implementation of REOMP is appropriate. We conclude that the proposed architecture is able to be used to neural network hardware implementation. To obtain the best performance of the architecture, the neural network model should make use of massively parallel neural processing of the previously processed data that is the case of feedforward neural networks.
Referências
DEHON, A. - The Density Advantage of Configurable Computing, IEEE Computer, Vol. 33, N. 4, 2000.
FUKUSHIMA, K. - Neural-network model for a mechanism of pattern recognition unaffected by shift in position - neocognitron, Trans. IECE Japan, vol.62-A, no. 10, 1979.
FUKUSHIMA, K.& Miyake, S. Neocognitron: A New Algorithm for Pattern Recognition Tolerant of Deformations and Shift in Position, Pattern Recognition, vol. 15, no.6, 1982.
FUKUSHIMA,.K. & WAKE, N. - lmproved Neocognitron with Bend-Detecting Cells, IEEE - International Joint Conference on Neural Networks, Baltimore, Maryland, 1992.
FUKUSHIMA,K.& TANIGAWA, M. - Use of Different Thresholds in Learning and Recognition, Neurocomputing, 11, 1996.
GOLDSTEIN, S. C.; SCHMIT, H.; BUDIU, M.; CADAMBI, S. Moe, M. & TAYLOR, R.R. PipeRench: A Reconfigurable Architecture and Compiler, IEEE Computer, Vol. 33, n. 4, 2000.
HWANG, K. ; TSENG, P & KlM, D.- An Orthogonal Multiprocessor for Parallel Scientific Computations, IEEE Trans. On Computers, Vol.38, N.1, 1989.
HWANG, K. Advanced Computer Architecture - Parallelism, Scalability, Programmability. McGrawHill, 1993.
MATSUMOTO, G. - The Brain and Brainway Computer - Proceedings of The 69 Fifth International Conference on Neural Information Processing, Kitakysushu, Japan, 1998.
MPI FORUM - MPI: A Message-Passing Interface Standard University of Tennessee, Knoxville, Tennessee, June 1995.
SAITO, J.H. & FUKUSHlMA, K. - Modular Structure of Neocognitron to Pattern Recognition, Proc. ICONIP'98, Fifth Int. Conf On Neural lnformation Processing, Kitakyushu, Japan, 1998.
SAlTO, J.H. - A Vector Orthogonal Multiprocessor NEOMP and its Use in Neural Network Mapping, Proceedings of the SBAC-PAD'99 11th Symposium on Computer Architecture and High Performance Computing, Natal, RN, Brazil, 1999.
