Yet Another Hardware Implementation of Modular Multiplication
Resumo
Modular multiplication is fundamental to several publickey cryptography systems such as the RSA encryption system. lt is also the most dominant part of the computation performed in such systems. The operation is time consuming for large operands. This paper examines the characteristics of yet another architecture to implement modular multiplication. An experimental modular multiplier prototype is described and some simulation results are presented.
Palavras-chave:
Modular Multiplication, Cryptosystems
Referências
Barrett, P., lmplementating the Rivest, Shamir and Aldham public-key encryption algorithm on standard digital signal processor, Proceedings of CRYPT0'86, Lecture Notes in Computer Science 263:311-323, Springer-Verlag, 1986.
Bewick, G. W., Fast multiplication algorithms and implementation, Ph.D. Thesis, Department of Electrical Engineering, Stanford University, United States of America, 1994.
Booth, A., A signed binary multiplication technique, Quarterly Journal of Mechanics and Applied Mathematics, pp. 236-240, 1951.
Brickell, E. F., A survey of hardware implementation of RSA, In G. Brassard, ed., Advances in Crypltology, Proceedings of CRYPT0'98, Lecture Notes in Computer Science 435:368-370, Springer-Verlag, 1989.
Eldridge, S. E. and Walter, C. D., Hardware implementation of Montgomery's Modular Multiplication Algorithm, IEEE Transactions on Computers, 42(6):619-624, 1993. 75
MacSorley, 0., High-speed arithmetic in binary computers, Proceedings of the IRE, pp. 67-91, 1961.
Rabaey, J., Digital integrated circuits: A design perspective, Prentice-Hall, 1995.
Rivest, R., Shamir, A. and Aldham, L., A method for obtaining digital signature and public-key cryptosystems, Communications of the ACM, 21: 120-126, 1978.
Shindler, V., High-speed RSA hardware based on low-power piplined logic, Ph.D. Thesis, Institut für Angewandte Informations-verarbeitung und Kommunikationstechnologie, Technishe Universitat Graz, January 1997.
Walter, C. D., Systolic modular multiplication, IEEE Transactions on Computers, 42(3):376-378, 1993.
Walter, C. D., A verification of Brickell's fast modular multiplication algorithm, International Journal of Computer Mathematics, 33:153:169.
Bewick, G. W., Fast multiplication algorithms and implementation, Ph.D. Thesis, Department of Electrical Engineering, Stanford University, United States of America, 1994.
Booth, A., A signed binary multiplication technique, Quarterly Journal of Mechanics and Applied Mathematics, pp. 236-240, 1951.
Brickell, E. F., A survey of hardware implementation of RSA, In G. Brassard, ed., Advances in Crypltology, Proceedings of CRYPT0'98, Lecture Notes in Computer Science 435:368-370, Springer-Verlag, 1989.
Eldridge, S. E. and Walter, C. D., Hardware implementation of Montgomery's Modular Multiplication Algorithm, IEEE Transactions on Computers, 42(6):619-624, 1993. 75
MacSorley, 0., High-speed arithmetic in binary computers, Proceedings of the IRE, pp. 67-91, 1961.
Rabaey, J., Digital integrated circuits: A design perspective, Prentice-Hall, 1995.
Rivest, R., Shamir, A. and Aldham, L., A method for obtaining digital signature and public-key cryptosystems, Communications of the ACM, 21: 120-126, 1978.
Shindler, V., High-speed RSA hardware based on low-power piplined logic, Ph.D. Thesis, Institut für Angewandte Informations-verarbeitung und Kommunikationstechnologie, Technishe Universitat Graz, January 1997.
Walter, C. D., Systolic modular multiplication, IEEE Transactions on Computers, 42(3):376-378, 1993.
Walter, C. D., A verification of Brickell's fast modular multiplication algorithm, International Journal of Computer Mathematics, 33:153:169.
Publicado
10/09/2001
Como Citar
NEDJAH, Nadia; MOURELLE, Luiza de Macedo.
Yet Another Hardware Implementation of Modular Multiplication. In: INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING (SBAC-PAD), 13. , 2001, Pirenópolis.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
2001
.
p. 70-75.
DOI: https://doi.org/10.5753/sbac-pad.2001.22195.
