Using the SGI Pro64 Open Source Compiler Infra-Structure for Teaching and Research
Resumo
Modem optimizing compilers are complex programs that require from tens to hundreds of people-years to be developed. Thus professors must use third-party compiler infra-structures to introduce students to compiler optimizations. Until recently only infra-structures developed at universities, research institutes, or by GNU were widely available for teaching. However, in May 2000, SGI made public the source code for Pro64, a highly optimized suite of compilers for the Intel Architecture 64 (IA-64) that is an evolution of the established MIPSPro suite of compilers. The use of a production-level compiler infra-structure for teaching is thus new. In this paper we report our experience using the Pro64 in a graduate compiler optimization class. We paired the study of the Pro64 with the use of IMPACT within Trimaran, and with performance studies conducted with the MIPSPro compilers. The students feedback indicate that they valued working with a state-of-the-art compiler infrastructure and studying open research topics for their class projects.
Palavras-chave:
Compiler Optimization, Code Generation, IA-64, Pro64, Trimaran, IMPACT, NUE, Ski, SUIF
Referências
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P. P. Tirumalai B. R. Rau, M. Lee and M. S. Schlansker. Register allocation for software pipelined loops. In Proceedings of the SIGPLAN '89 Conference on Programming language design and implementation. pages 283-29, San Francisco, CA. June 1992.
F. Chow, S. Chan, R. Kennedy, S.-M. Liu, R. Lo, and P. Tu. A new algorithm for partial redundancy elimination based on SSA form. In Proc. of SIGPLAN 97 Conference on Programming Language Deisng and lmplementation, pages 273-286, May 1997.
F. C. Chow and J. L. Hennessy. The priority-based coloring approach to register allocation. ACM Transactions on Programming Languages and Systems, 12(4):501-536, October 1990.
G. J. Chaitin. Register allocation and spilling via graph coloring. In Proceedings of the SIGPLAN '82 Symposium on Compiler Construction, pages 98-105, June 1982.
O. Callahan and B. Koblenz. Register allocation via hierarchical graph coloring. In Proceedings of the SIGPLAN'89 Conference on Programming language design and implementation, pages 192-203, Toronto, Canada, June 1991.
P. P. Chang, S. A. Mahlke, W. Y. Chen, N. J. Walter, and W.-M. H. Hwu. IMPACT: An architectural framework for multiple-instruction-issue processors. In 18th lnternational Symposium on Computer Architectutre, pages 266-275, Toronto, Canada, May 1991.
Hewlet-Packard Co. ia-64 linux developer tools. http://www.software.hp.com/LIA64.
Hewlet-Packard Co. Ski IA-64 Simulalor Reference Manual, rev. 1.01 edilion, April 2000.
J. C. Oehnert. P. H.-T. Hsu, and J. P. Brau. Overlapped loop support in the cydra 5. In Proceedings of the Third International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 26-38, Boston. MA, April 1989.
J. C. Oehnert and R. A. Towle. Compiling for cydra 5. The Journal of Supercomputing, (7): 181-227, 1993.
G. R. Gao, J. N. Amaral, J. Oehnert, and R. Towle. The SGI pro64 compiler infrastructure: A tutorial. Tutorial presented at the International Conference on Parallel Architecture and Compilation Techniques (PACT2000), October 2000.
E. Gagnon and L. Hendren. SableVM: A research framework for the efficient execution of java bytecode. In Java Virtual Machine Research and Technology Symposium, Monterey. CA. April 2001.
Silicon Graphics Inc. SpeedShop user's guide. Technical Report 007-3311 -006, Mountain View, CA, 1999. available at http://techpubs.sgi.com/library.
V. Kathail, M. S. Schlansker, and B. R. Rau. HPL-PD architecture specification: Version 1.1. Technical Report HPL-93- 80(R.1), Hewlell Packard, Palo Alto, CA, FEb. 2000.
ReaCT-ILP Laboratory. Trimaran: An infrastructure for research in instruction-level parallelism. http://www.trimaran.org.
S. A. Mahlke. E.rploiting lnstruction Level Parallelism in the Presence of Conditional Branches. PhD thesis, University of lllinois at Urbana-Champaign, 1996.
K. Kennedy P. Briggs, K. D. Cooper and L. Torczon. Coloring heuristics for register allocation. In Proceedings of the SIGPLAN '89 Conference on Programming Language design and implementation, pages 275 - 284, Portland, OR, June 1989.
B. R. Rau, O. W. L. Yen, W. Yen, and R. A. Towle. The cydra 5 departmental supercomputer - design philosophies, decisions, and trade-offs. IEEE Computer, pages 12-35, January 1989.
A. Stoutchinin, J. N. Amaral, G. R. Gao, S. Jain J. Dehnert, and A. Douillet. Speculative pointer prefetching of induction pointers. In Reinhard Wilhelm, editor, Compiler Construction 2001 - European Joint Conferences on Theory and Practice of Software, Lecture Notes in Computer Science, pages 289- 303, Genova, Italy, April 2001. Springer-Verlang.
E. Schnarr and J. R. Larus. Fast out-of-order processor simulation using memoization. In 8th international conference on Architectural support for programming languages and operating systems, pages 283-294, San Jose, CA, October 1998.
M. S. Schlansker and B. R. Rau. EPIC: Explicitly parallel instruction computing. Compuler, 33(2):37-45, Feb 2000.
M. E. Wolf, O. E. Maydan, and D.-K. Chen. Combining loop transformations considering caches and scheduling. In Proceedings of the 29th annual IEEE/ACM international symposium on Microarchitecture, pages 274-286, Paris, France, December 1996.
GNU compiler collection. http://gcc.gnu.org.
High performance fortran (HPF). http://www.crpc.rice.edu/HPFF/
Real time compilation technology and instruction level parallelism. http://www.cs.nyu.edu/react-ilp/. New York University.
SableVM: A bytecode interpreter. http://www.sablevm.org.
The simplescalar architectural research tool set, version 2.0. http://www.cs.wisc.edu/mscalar/simplescalar.html. University of Wisconsin.
The SUIF 2 compiler system. http://suif.stanford.edu/suif/suif2.
S. Aditya, V. Kathail, and B. R. Rau. Elcor's machine description system: Version 3.0. Technical Report HPL-98-128, Hewlett-Packard Laboratories, Palo Alto, CA, July 1998.
P. P. Tirumalai B. R. Rau, M. Lee and M. S. Schlansker. Register allocation for software pipelined loops. In Proceedings of the SIGPLAN '89 Conference on Programming language design and implementation. pages 283-29, San Francisco, CA. June 1992.
F. Chow, S. Chan, R. Kennedy, S.-M. Liu, R. Lo, and P. Tu. A new algorithm for partial redundancy elimination based on SSA form. In Proc. of SIGPLAN 97 Conference on Programming Language Deisng and lmplementation, pages 273-286, May 1997.
F. C. Chow and J. L. Hennessy. The priority-based coloring approach to register allocation. ACM Transactions on Programming Languages and Systems, 12(4):501-536, October 1990.
G. J. Chaitin. Register allocation and spilling via graph coloring. In Proceedings of the SIGPLAN '82 Symposium on Compiler Construction, pages 98-105, June 1982.
O. Callahan and B. Koblenz. Register allocation via hierarchical graph coloring. In Proceedings of the SIGPLAN'89 Conference on Programming language design and implementation, pages 192-203, Toronto, Canada, June 1991.
P. P. Chang, S. A. Mahlke, W. Y. Chen, N. J. Walter, and W.-M. H. Hwu. IMPACT: An architectural framework for multiple-instruction-issue processors. In 18th lnternational Symposium on Computer Architectutre, pages 266-275, Toronto, Canada, May 1991.
Hewlet-Packard Co. ia-64 linux developer tools. http://www.software.hp.com/LIA64.
Hewlet-Packard Co. Ski IA-64 Simulalor Reference Manual, rev. 1.01 edilion, April 2000.
J. C. Oehnert. P. H.-T. Hsu, and J. P. Brau. Overlapped loop support in the cydra 5. In Proceedings of the Third International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 26-38, Boston. MA, April 1989.
J. C. Oehnert and R. A. Towle. Compiling for cydra 5. The Journal of Supercomputing, (7): 181-227, 1993.
G. R. Gao, J. N. Amaral, J. Oehnert, and R. Towle. The SGI pro64 compiler infrastructure: A tutorial. Tutorial presented at the International Conference on Parallel Architecture and Compilation Techniques (PACT2000), October 2000.
E. Gagnon and L. Hendren. SableVM: A research framework for the efficient execution of java bytecode. In Java Virtual Machine Research and Technology Symposium, Monterey. CA. April 2001.
Silicon Graphics Inc. SpeedShop user's guide. Technical Report 007-3311 -006, Mountain View, CA, 1999. available at http://techpubs.sgi.com/library.
V. Kathail, M. S. Schlansker, and B. R. Rau. HPL-PD architecture specification: Version 1.1. Technical Report HPL-93- 80(R.1), Hewlell Packard, Palo Alto, CA, FEb. 2000.
ReaCT-ILP Laboratory. Trimaran: An infrastructure for research in instruction-level parallelism. http://www.trimaran.org.
S. A. Mahlke. E.rploiting lnstruction Level Parallelism in the Presence of Conditional Branches. PhD thesis, University of lllinois at Urbana-Champaign, 1996.
K. Kennedy P. Briggs, K. D. Cooper and L. Torczon. Coloring heuristics for register allocation. In Proceedings of the SIGPLAN '89 Conference on Programming Language design and implementation, pages 275 - 284, Portland, OR, June 1989.
B. R. Rau, O. W. L. Yen, W. Yen, and R. A. Towle. The cydra 5 departmental supercomputer - design philosophies, decisions, and trade-offs. IEEE Computer, pages 12-35, January 1989.
A. Stoutchinin, J. N. Amaral, G. R. Gao, S. Jain J. Dehnert, and A. Douillet. Speculative pointer prefetching of induction pointers. In Reinhard Wilhelm, editor, Compiler Construction 2001 - European Joint Conferences on Theory and Practice of Software, Lecture Notes in Computer Science, pages 289- 303, Genova, Italy, April 2001. Springer-Verlang.
E. Schnarr and J. R. Larus. Fast out-of-order processor simulation using memoization. In 8th international conference on Architectural support for programming languages and operating systems, pages 283-294, San Jose, CA, October 1998.
M. S. Schlansker and B. R. Rau. EPIC: Explicitly parallel instruction computing. Compuler, 33(2):37-45, Feb 2000.
M. E. Wolf, O. E. Maydan, and D.-K. Chen. Combining loop transformations considering caches and scheduling. In Proceedings of the 29th annual IEEE/ACM international symposium on Microarchitecture, pages 274-286, Paris, France, December 1996.
GNU compiler collection. http://gcc.gnu.org.
High performance fortran (HPF). http://www.crpc.rice.edu/HPFF/
Real time compilation technology and instruction level parallelism. http://www.cs.nyu.edu/react-ilp/. New York University.
SableVM: A bytecode interpreter. http://www.sablevm.org.
The simplescalar architectural research tool set, version 2.0. http://www.cs.wisc.edu/mscalar/simplescalar.html. University of Wisconsin.
The SUIF 2 compiler system. http://suif.stanford.edu/suif/suif2.
Publicado
10/09/2001
Como Citar
AMARAL, José Nelson; BARTON, Christopher; MACDONELL, Andrew C.; MCNAUGHTON, Matthew.
Using the SGI Pro64 Open Source Compiler Infra-Structure for Teaching and Research. In: INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING (SBAC-PAD), 13. , 2001, Pirenópolis.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
2001
.
p. 206-213.
DOI: https://doi.org/10.5753/sbac-pad.2001.22210.
