Proposal for a High-Performance, Scalable Multiprocessor

  • José Eduardo Morreira University of Illinois
  • João Antônio Zuffo USP
  • Sérgio Takeo Kofuji USP

Resumo


This report describes a proposed architecture for a massively parallel, shared memory computer, using commercially available microprocessors (DEC Alphas). The architecture is scalable from 4 processors to 65536 processors. Each processor has a peak performance of 200Mflops, and therefore this proposed architecture allows us to build systems with peak performance greater than 10 Tflops. Four processors are organized as a tightly coupled multiprocessing cluster. Multiple clusters (up to 8) can share a host, and multiple hosts can be used to build larger systems. Clusters communicate by means of a scalable interconnection network, that allows processors from one cluster to access the memory in a different cluster, thus providing a single memory space. Coherent caches are used to both reduce and hide the latency of inter-cluster communication.

Referências

Anant Agarwal, Richard Simont, John Hennessy, and Mark Horowitz. An Evaluation of Directory Schemes for Cache Coherence. In Proceedings of the 15th Annual International Symposium on Computer Architecture, Honolulu, Hawaii, 1988.

Eugene D. Brooks. Massively Parallel Computing. In The 1992 MPCI Yearly Report: Harnessing the Killer Micros. Lawrence Livermore National Laboratory, August, 1992.

Digital Equipment Corporation, Maynard, Massachusetts. Alpha Architecture Handbook - Preliminary Edition, 1992.

Susan J. Eggers and Randy H. Katz. A Characterization of Sharing in Parallel Programs and Applications to Coherence Protocol Evaluation. In Proceedings of the 15th Annual International Symposium on Computer Architecture, Honolulu, Hawaii, 1988.

Kai Hwang and Fayé A. Briggs. Computer Architecture and Parallel Processing. McGraw-Hill, 1984.

David V. James. SCI (Scalable Coherent Interface) Cache Coherence. Cache and Interconnect Architectures in Multiprocessors, Dubois and Thakkar editors, 1989.

Eric McIntosh. Benchmarking Computers for HEP. Technical report, CERN School of Computing. L'Aquila, Italy, 1992.

José E. Moreira. Multiple Omega Networks for Parallel Processing. In Proceedings of the IV Brazilian Symposium on Computer Architecture - High Performance Processing. São Paulo, Brazil, October 26-29, 1992.

The FY 1992 U.S. Research and Developmente Program. Grand Challenges: High Performance Computing and Communications, 1992. A Report by the Committee on Physical, Mathematical, and Engineering Sciences, Federal Coordinating Council for Science, Engineering, and Technology, Office of Science and Technology Policy.

Sun Microsystems Computer Corporation, Mountain View, California. SPA RCcenter 2000 (sales brochure), 1992.
Publicado
07/09/1993
MORREIRA, José Eduardo; ZUFFO, João Antônio; KOFUJI, Sérgio Takeo. Proposal for a High-Performance, Scalable Multiprocessor. In: INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING (SBAC-PAD), 5. , 1993, Florianópolis/SC. Anais [...]. Porto Alegre: Sociedade Brasileira de Computação, 1993 . p. 136-149. DOI: https://doi.org/10.5753/sbac-pad.1993.23028.