Proposal for a High-Performance, Scalable Multiprocessor

• José Eduardo Morreira University of Illinois
• João Antônio Zuffo USP
• Sérgio Takeo Kofuji USP

DOI: https://doi.org/10.5753/sbac-pad.1993.23028

Resumo

This report describes a proposed architecture for a massively parallel, shared memory computer, using commercially available microprocessors (DEC Alphas). The architecture is scalable from 4 processors to 65536 processors. Each processor has a peak performance of 200Mflops, and therefore this proposed architecture allows us to build systems with peak performance greater than 10 Tflops. Four processors are organized as a tightly coupled multiprocessing cluster. Multiple clusters (up to 8) can share a host, and multiple hosts can be used to build larger systems. Clusters communicate by means of a scalable interconnection network, that allows processors from one cluster to access the memory in a different cluster, thus providing a single memory space. Coherent caches are used to both reduce and hide the latency of inter-cluster communication.

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