Uma Avaliação de Estruturas de Memória para Multiprocessadores
Resumo
Este trabalho compara diferentes organizações de memória para multiprocessadores. A contribuição de memórias locais e memórias cache privadas para aumento de desempenho é considerada. O estudo abrange sistemas com diferentes estruturas de interconexão: barramentos compartilhados, redes "crossbar” e redes de múltiplos estágios. O modelo porposto por Patel é extendido e aplicado a diferentes estruturas de memória. A análise indica que o miss ratio da cache é, entre os parâmetros do modelo, aquele que mais influencia o desempenho relativo das estruturas de memória consideradas. Os resultados indicam que a organização com cache e memória local é a que apresenta melhor desempenho, que é, no entanto, próximo ao apresentado pela organização que contém apenas a cache.
Referências
Archibald, J.; Baer, J.L.: An Economical Solution on the Cache Coherence Problem. 11th Ann. Int. Symp. Comp. Arch., June 1984, pp. 335-362.
Archibald, J.; Baer, J.L.: An Evaluation of Cache Coherence Solutions in Shared-Bus Multiprocessors. Tech. Rep. 85-10-05, Department of Computer Science, University of Washington, Seattle, WA 98185.
Bhandarkar, D.P.: Analysis of Memory Interference in Multiprocessors. IEEE Trans. Comp., Vol. C-24, Sept. 1975, pp. 897-908.
Bitar, P.; Despain, A.M.: Multiprocessor Cache Synchronization, Issues, Innovations, Evolution. 13th Ann. Int. Symp. Comp. Arch., June 1986, pp. 424-433.
Bode, A.; Handler, W.: Rechnerarchitektur II, Strukturen. Springer Verlag, 1983.
Censier,L.M.; Feautrier, P.: A New Solution to Coherence Problems in Multicache Systems. IEEE Trans. Comp., Vol. C-27, No. 12, Dec., 1978, pp. 1112-1118.
Dubois, M.; Briggs, F.A.: Effects of Cache Coherency in Multiprocessors. IEEE Trans. Comp., Vol. C-31, No. 11, Nov. 1982, pp. 312-328.
Dubois, M.: Effect of Invalidations on the Hit Ratio of Cache-based Multiprocessors, Proc. Int. Conf. Parallel Processing, 1987, pp. 255-257.
Feitosa, R. Q.: Speicherstrukturen von Speichergekoppelten Multiprozessoren, Arbeitsberichte des IMMD, Universitaet Erlangen Nuernberg, Tese de Doutorado.
Feitosa, R. Q.: O Problema de Coerência de Memórias Cache Privadas em Grandes Multiprocessadores para Aplicações Numéricas: Uma Nova Solução, Anais do XVII SEMISH, 1990.
Kaplan, K.R.; Winder, R.O.: Cache based Computer Systems. Computer, Mar. 1973, pp. 30-36.
Katz, R.H.; Eggers, S.J.; Wood, D.A.; Perkins, D.L.; Sheldon, R.G.: Implementing Cache Consistency Protocol, 12th Int. Ann. Symp. Comp. Arch., June 1985, pp. 276283.
MacGregor, D.; Mothersole, D.; Moyer, B.: The Motorola 68020. IEEE Micro, Vol. 4, No. 4, Aug. 1984, pp. 101118.
Patel, J.H.: Performance of Processor-Memory Interconnection for Multiprocessors. IEEE Trans. Comp., Vol. C-30, Oct. 1981, pp. 771-780.
Patel, J.H.: Analysis of Multiprocessors with Private Cache Memories. IEEE Trans. Comp., Vol. C-31, April 1982, pp. 296-304.
Pfister, G.F.; Brantley, W.C.; George, D.A.; Harvey, S.L.; Kleinfelder, W.J.; McAuliffe, K.P.; Melton, E.A.; Norton, V.A.; Weiss, J.: The IBM Research Parallel Processor Prototype (RP3): Introduction and Architecture. 12th Ann. Int. Symp. Comp. Arch., 1985, pp. 764-771.
Ravi, C.V.: On the Bandwidth and Interference in Interleaved Memory Systems. IEEE Trans. Comp., Vol. C- 21, Aug. 1972, pp. 899-901.
Siegel, H.J.: Interconnection Network for Large-Scale Parallel Processing, Lexington Books, 1985.
Smilauer, B.: General Model for Memory Interference in Multiprocessors and Mean Value Analysis. IEEE Trans. Comp., Vol. C-34, No. 8, Aug. 1985, pp. 744-751.
Smith, A.J.: Cache Memories. Computing Surveys 14, Sept. 1982, pp. 473-530.
Smith, A.J.: Cache Evaluation and the Impact of Workload Choice. 12th Ann. Int. Symp. Comp. Arch., 1985, pp. 6473.
Vernon, M.K.; Holliday, M.A.; Performance Analyses of Multiprocessor Cache Consistency Protocols Using Generalized Timed Petri Nets. Performance Evaluation Review, Vol. 14, No. 1, May 1986, pp. 9-17.
Wood, D.A., et al.: A In-Cache Address Translation Mechanism. 13th Ann. Int. Symp. Comp. Arch., June 1986, pp. 365-385.
Yen, D.W.L.; Patel, J.H.; Davidson, E.S.: Memory Interference in Synchronous Multiprocessor Systems. IEEE Trans. Comp., Vol. C-31, No. 11, Nov. 1982, pp. 1116-1121.
Archibald, J.; Baer, J.L.: An Evaluation of Cache Coherence Solutions in Shared-Bus Multiprocessors. Tech. Rep. 85-10-05, Department of Computer Science, University of Washington, Seattle, WA 98185.
Bhandarkar, D.P.: Analysis of Memory Interference in Multiprocessors. IEEE Trans. Comp., Vol. C-24, Sept. 1975, pp. 897-908.
Bitar, P.; Despain, A.M.: Multiprocessor Cache Synchronization, Issues, Innovations, Evolution. 13th Ann. Int. Symp. Comp. Arch., June 1986, pp. 424-433.
Bode, A.; Handler, W.: Rechnerarchitektur II, Strukturen. Springer Verlag, 1983.
Censier,L.M.; Feautrier, P.: A New Solution to Coherence Problems in Multicache Systems. IEEE Trans. Comp., Vol. C-27, No. 12, Dec., 1978, pp. 1112-1118.
Dubois, M.; Briggs, F.A.: Effects of Cache Coherency in Multiprocessors. IEEE Trans. Comp., Vol. C-31, No. 11, Nov. 1982, pp. 312-328.
Dubois, M.: Effect of Invalidations on the Hit Ratio of Cache-based Multiprocessors, Proc. Int. Conf. Parallel Processing, 1987, pp. 255-257.
Feitosa, R. Q.: Speicherstrukturen von Speichergekoppelten Multiprozessoren, Arbeitsberichte des IMMD, Universitaet Erlangen Nuernberg, Tese de Doutorado.
Feitosa, R. Q.: O Problema de Coerência de Memórias Cache Privadas em Grandes Multiprocessadores para Aplicações Numéricas: Uma Nova Solução, Anais do XVII SEMISH, 1990.
Kaplan, K.R.; Winder, R.O.: Cache based Computer Systems. Computer, Mar. 1973, pp. 30-36.
Katz, R.H.; Eggers, S.J.; Wood, D.A.; Perkins, D.L.; Sheldon, R.G.: Implementing Cache Consistency Protocol, 12th Int. Ann. Symp. Comp. Arch., June 1985, pp. 276283.
MacGregor, D.; Mothersole, D.; Moyer, B.: The Motorola 68020. IEEE Micro, Vol. 4, No. 4, Aug. 1984, pp. 101118.
Patel, J.H.: Performance of Processor-Memory Interconnection for Multiprocessors. IEEE Trans. Comp., Vol. C-30, Oct. 1981, pp. 771-780.
Patel, J.H.: Analysis of Multiprocessors with Private Cache Memories. IEEE Trans. Comp., Vol. C-31, April 1982, pp. 296-304.
Pfister, G.F.; Brantley, W.C.; George, D.A.; Harvey, S.L.; Kleinfelder, W.J.; McAuliffe, K.P.; Melton, E.A.; Norton, V.A.; Weiss, J.: The IBM Research Parallel Processor Prototype (RP3): Introduction and Architecture. 12th Ann. Int. Symp. Comp. Arch., 1985, pp. 764-771.
Ravi, C.V.: On the Bandwidth and Interference in Interleaved Memory Systems. IEEE Trans. Comp., Vol. C- 21, Aug. 1972, pp. 899-901.
Siegel, H.J.: Interconnection Network for Large-Scale Parallel Processing, Lexington Books, 1985.
Smilauer, B.: General Model for Memory Interference in Multiprocessors and Mean Value Analysis. IEEE Trans. Comp., Vol. C-34, No. 8, Aug. 1985, pp. 744-751.
Smith, A.J.: Cache Memories. Computing Surveys 14, Sept. 1982, pp. 473-530.
Smith, A.J.: Cache Evaluation and the Impact of Workload Choice. 12th Ann. Int. Symp. Comp. Arch., 1985, pp. 6473.
Vernon, M.K.; Holliday, M.A.; Performance Analyses of Multiprocessor Cache Consistency Protocols Using Generalized Timed Petri Nets. Performance Evaluation Review, Vol. 14, No. 1, May 1986, pp. 9-17.
Wood, D.A., et al.: A In-Cache Address Translation Mechanism. 13th Ann. Int. Symp. Comp. Arch., June 1986, pp. 365-385.
Yen, D.W.L.; Patel, J.H.; Davidson, E.S.: Memory Interference in Synchronous Multiprocessor Systems. IEEE Trans. Comp., Vol. C-31, No. 11, Nov. 1982, pp. 1116-1121.
Publicado
07/11/1990
Como Citar
FEITOSA, Raul Queiroz.
Uma Avaliação de Estruturas de Memória para Multiprocessadores. In: INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING (SBAC-PAD), 3. , 1990, Rio de Janeiro/RJ.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
1990
.
p. 330-344.
DOI: https://doi.org/10.5753/sbac-pad.1990.23127.
