gem5-ndp: Near-Data Processing Architecture Simulation From Low Level Caches to DRAM

• João Vieira INESC-ID / Instituto Superior Técnico / University of Lisbon
• Nuno Roma INESC-ID / Instituto Superior Técnico / University of Lisbon
• Gabriel Falcao Instituto de Telecomunicações / University of Coimbra
• Pedro Tomás INESC-ID / Instituto Superior Técnico / University of Lisbon

Resumo

Unlike standard accelerators, the performance of Near-Data Processing (NDP) devices highly depends on the operation of the surrounding system, namely, the Central Processing Unit (CPU) and the memory hierarchy. Therefore, to accurately evaluate the gain provided by such devices, the entire processing system must be considered. Recent proposals redesigned existing architectural simulators to estimate the performance of NDP devices. However, the conclusions that can be drawn from using these frameworks are limited, and they fail to provide full support to simulate these devices (e.g., most simulators do not allow simultaneous operation of the CPU and the NDP device). In this paper, a novel framework (called gem5-ndp) based on the gem5 architectural simulator is proposed, providing full support to the development, validation, and evaluation of novel NDP architectures. To illustrate the process of developing and integrating an NDP device with a processing system using the proposed framework, as well as to demonstrate its viability and benefits, two case studies are also proposed and thoroughly discussed. gem5-ndp significantly improves the performance evaluation confidence of NDP devices with results showing that classical approaches lead to a deviation of up to 54.9 % when compared with results obtained with gem5-ndp.

Palavras-chave: Near-Data Processing, Multi-Level Memory Hierarchies, Simulation Framework, Data-Parallel Processing