The eDRAM based L3-cache of the BlueGene/L supercomputer processor node

• M. Ohmacht IBM Thomas J. Watson Research Center
• D. Hoenicke IBM Thomas J. Watson Research Center
• R. Haring IBM Thomas J. Watson Research Center
• A. Gara IBM Thomas J. Watson Research Center

Resumo

BlueGene/L is a supercomputer consisting of 64K dual-processor system-on-a-chip compute nodes, capable of delivering an arithmetic peak performance of 5.6Gflops per node. To match the memory speed to the high compute performance, the system implements an aggressive three-level on-chip cache hierarchy for each node. The implemented hierarchy offers high bandwidth and integrated prefetching on cache hierarchy levels 2 and 3 to reduce memory access time. The integrated L3-cache stores a total of 4MB of data, using multibank embedded DRAM. The 1024 bit wide data port of the embedded DRAM provides 22.4GB/s bandwidth to serve the speculative prefetching demands of the two processor cores and the Gigabit Ethernet DMA engine.

Palavras-chave: Supercomputers, Random access memory, Delay, System-on-a-chip, Bandwidth, Ethernet networks, Computer architecture, High performance computing, Prefetching, Arithmetic