A Speculative Trace Reuse Architecture with Reduced Hardware Requirements

• Mauricio L. Pilla UCPel
• Bruce R. Childers University of Pittsburgh
• Amarildo T. Da Costa IME
• Felipe M. G. Franca UFRJ
• Philippe O. A. Navaux UFRGS

Abstract

Trace reuse is an effective way of improving the performance of superscalar processors by skipping the execution of a sequence of instructions with known input and output values. However, the extra hardware complexity is of special concern when implementing such mechanisms. In this paper, we describe ways to reduce these requirements for Reuse through Speculation on Traces (RST). RST combines instruction and trace reuse with value prediction in an integrated mechanism to provide missing trace inputs when execution reaches the beginning of a trace. Speculatively reused traces do not consume resources in the execution pipeline, as they are not executed. In this paper, we study the effects of constraining reuse tables to effectively reduce the number of reuse candidates and comparisons. We compare our approach to instruction reuse, trace reuse and value prediction. We show that RST reuses more instructions and has better performance than traditional trace reuse, with an average speedup over a baseline without reuse of 1.21.

Keywords: Hardware, Pipelines, Computer architecture, Computer science, High performance computing, Impedance, Degradation, Clocks, Parallel processing, Computer aided instruction