Queue Register File Optimization Algorithm for QueueCore Processor

• Arquimedes Canedo University of Electro-Communications
• Ben Abderazek University of Electro-Communications
• Masahiro Sowa University of Electro-Communications

Resumo

The queue computation model offers an attractive alternative for high-performance embedded computing given its characteristics of short instructions and high instruction level parallelism. A queue-based processor uses a FIFO queue to read and write operands through hardware pointers located at the head and tail of the queue. Queue length is the number of elements stored between the head and the tail pointers during computations. We have found that 95% of the statements in integer applications require a queue length of less than 32 words. The remaining 5% requires larger queue length sizes up to 230 queue words. In this paper we propose a compiler technique to optimize the queue utilization for the hungry statements that require a large amount of queue. We show that for SPEC CINT95 benchmarks, our technique optimizes the queue length without decreasing parallelism. However, our optimization has a penalty of a slight increase in code size.

Palavras-chave: Registers, Tail, Hardware, Computer architecture, Embedded computing, Computational modeling, Parallel processing, High performance computing, Computer aided instruction, Program processors