An Intelligent Mechanism to Explore a Two-Level Cache Hierarchy Considering Energy Consumption and Time Performance

• Abel G. Silva-Filho UPE
• Carmelo J. A. Bastos-Filho UPE
• Ricardo M. F. Lima UPE
• Davi M.A. Falcao UPE
• Filipe R. Cordeiro UPE
• Marilia P. Lima UPE

Abstract

Cache memory hierarchy contributes positively to system performance. Moreover, tuning cache architectures in platforms for embedded applications can dramatically reduce energy consumption. This paper presents an automated method for adjusting two-level cache memory hierarchy intended for data caches in order to reduce energy consumption and improve the performance of embedded applications. We propose an automated mechanism called TEMGA (Two-level cache Exploration Mechanism based on Genetic Algorithm), to determine the suitable cache hierarchy configuration by exploring a small part of search space. In our experiments, we applied the proposed mechanism to 12 different benchmarks from the MiBench suite. The results show an average reduction of about 15% in the energy consumption for data caches when compared to existing heuristics and a reduction of 5 times in the number of cycles needed to execute applications from Mibench Benchmark suite.

Keywords: Energy consumption, Computer architecture, Genetic algorithms, Space exploration, Cache memory, Microprocessors, Embedded computing, High performance computing, Computational intelligence, System performance