An Optimization Mechanism Intended for Two-Level Cache Hierarchy to Improve Energy and Performance Using the NSGAII Algorithm

• Abel G. Silva-Filho UPE
• Carmelo J. A. Bastos-Filho UPE
• Davi M. A. Falcão UPE
• Filipe R. Cordeiro UPE
• Rodrigo M. C. S. Castro UPE

Resumo

Tuning cache architectures in MPSoC platforms for embedded applications can dramatically reduce energy consumption. This paper presents a design tool for adjusting a two-level cache memory hierarchy that uses a fast non-dominated sorting algorithm (NSGAII) in order to provide decision support capabilities. It aims to reduce energy consumption and improve the performance of embedded applications. This optimization mechanism finds the best set of cache configurations (Pareto-Front) and offers support to the architecture designer in order to provide a set of non-dominated solutions for a decision maker. In our experiments, we applied the proposed mechanism to 12 different applications from the MiBench benchmark suite. Furthermore, the simulation results showed that the solutions found by our proposal are comparable to the results of other techniques and, for 67% of the analyzed cases, the efficiency of the mechanism was achieved.

Palavras-chave: Computer architecture, Energy consumption, Space exploration, Embedded computing, Design optimization, Algorithm design and analysis, Genetic algorithms, High performance computing, Cache memory, Sorting, Low Power, Optimization Mechanism, Memory Cache, ASGAII Algorithm, Two-Level Cache Hierarchy