A Software Transactional Memory System for an Asymmetric Processor Architecture

  • Felipe Goldstein UNICAMP
  • Alexandro Baldassin UNICAMP
  • Paulo Centoducatte UNICAMP
  • Rodolfo Azevedo UNICAMP
  • Leonardo A. G. Garcia Linux Technology Center / IBM

Resumo


Due to the advent of multi-core processors and the consequent need for better concurrent programming abstractions, new synchronization paradigms have emerged. A promising one, known as software transactional memory (STM), aims to use transactions as the key synchronization mechanism to ease program development as well as increase its performance. Many (if not all) of the current STM implementations target homogeneous architectures. In this paper we describe an implementation of an STM system for an asymmetric architecture, the Cell BE. We evaluated our Transactional Software Cache (TSC) mechanism using a well-known micro-benchmark (IntSet) and the Genome application from STAMP. The results show that an STM implementation for the Cell architecture is feasible if the shared-memory programming model is adopted. When compared to a conventional lock-based implementation, the STM version of Genome obtained a performance gain of 84% and 24% with large and small input sets, respectively.
Palavras-chave: Software systems, Computer architecture, Multicore processing, Genomics, Bioinformatics, Performance gain, Programming profession, High performance computing, Software performance, Application software, Transactional Memory, Software Cache, Asymmetric Architecture
Publicado
29/10/2008
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GOLDSTEIN, Felipe; BALDASSIN, Alexandro; CENTODUCATTE, Paulo; AZEVEDO, Rodolfo; GARCIA, Leonardo A. G.. A Software Transactional Memory System for an Asymmetric Processor Architecture. In: INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING (SBAC-PAD), 20. , 2008, Campo Grande/MS. Anais [...]. Porto Alegre: Sociedade Brasileira de Computação, 2008 . p. 175-182.