List Scheduling in Embedded Systems under Memory Constraints

  • Paul-Antoine Arras Inria Bordeaux Sud-Ouest
  • Didier Fuin STMicroelectronics
  • Emmanuel Jeannot Inria Bordeaux Sud-Ouest
  • Arthur Stoutchinin STMicroelectronics
  • Samuel Thibault Inria Bordeaux Sud-Ouest

Abstract


Video decoding and image processing in embedded systems are subject to strong resource constraints, particularly in terms of memory. List-scheduling heuristics with static priorities (HEFT, SDC, etc.) being the often-cited solutions due to both their good performance and their low complexity, we propose a method aimed at introducing the notion of memory into them. Moreover, we show that through appropriate adjustment of task priorities and judicious resort to insertion-based policy, speedups up to 20% can be achieved. Lastly, we show that our technique allows to prevent deadlock and to substantially reduce the required memory footprint compared to classic list-scheduling heuristics.
Keywords: Memory management, Schedules, Processor scheduling, System recovery, Computational modeling, System-on-chip, Embedded systems, Task graphs, scheduling, memory, system on chip, video decoding
Published
2013-10-23
How to Cite

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ARRAS, Paul-Antoine; FUIN, Didier; JEANNOT, Emmanuel; STOUTCHININ, Arthur; THIBAULT, Samuel. List Scheduling in Embedded Systems under Memory Constraints. In: INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING (SBAC-PAD), 25. , 2013, Porto de Galinhas/PE. Anais [...]. Porto Alegre: Sociedade Brasileira de Computação, 2013 . p. 152-159.