Automatic Generation of Custom Parallel Processors for Morphological Image Processing
Resumo
Image processing applications are well established in modern society, presenting continuous advances and challenges. One of its fundamental techniques is morphological image processing, a nonlinear branch in image processing, which have high performance requirements. Although usually demanding for general purpose processors, it presents a high degree of achievable parallelism, making FPGA based platforms suitable candidates for this task. However, ad-hoc FPGA implementations of specialized functions to be applied to images of varying dimensions suffers from long development times and lack of flexibility. In the literature, several intelligent systems using mathematical morphology were proposed for image processing tasks, where their main bottleneck is to evaluate the fitness function for image training pairs. In this context usually sets of low spatial resolution image pairs for the training process are used. However, the fitness evaluation timing for those problems is very demanding in practice. The scheme presented in this paper aims to tackle these limitations, proposing a strategy to automatically generate custom parallel processors for morphological image processing. The proposed scheme consists of a general architecture, and a software tool used to generate custom processors. The scheme is implemented using Matlab, which generates synthesizable Verilog structures based on a few textual parameters of morphological operations and image dimensions. Experimental results have shown the method effectiveness, generating custom processors capable to perform morphological transformations on images.
Palavras-chave:
Program processors, Hardware design languages, Morphological operations, Hardware, Programming, Field programmable gate arrays
Publicado
22/10/2014
Como Citar
PEDRINO, Emerson Carlos; FERNANDES, Marcio Merino.
Automatic Generation of Custom Parallel Processors for Morphological Image Processing. In: INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING (SBAC-PAD), 26. , 2014, Paris/FR.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
2014
.
p. 176-181.
