Unifying Router Power Gating with Data Placement for Energy-Efficient NoC

• Yuho Jin New Mexico State University

Resumo

Network-on-Chip (NoC) is a critical hardware supporting on-chip data movement in multicore and many-core processors. Data movement is predicted to become a major power-consuming operation compared to computation as the technology scales. This paper shows that unifying router power gating with data placement significantly reduces dynamic and static power needed for moving data in NoC for memory hierarchy. Region-based data placement enables to localize private data traffic and to concentrate shared data traffic in one region of NoC, which shapes traffic in a well-behaved way and increases power gating opportunities. In this regard, a dimensionally power-gated router with a region-based routing algorithm is proposed to reduce router static power and performance/energy overheads in power gating. Full-system evaluation using SPEComp benchmarks shows that the dynamic power gating management achieves NoC power savings by 46% and the static power gating management improves energy-efficiency by 20%.

Palavras-chave: Multicore processing, Hardware, System-on-chip, Power demand, Program processors, Shape, Network-on-Chip, power gating, data placement