Communication Latency Evaluation on a Software-Defined Network-on-Chip

  • Raul Silveira Silva UFRN
  • Patricia Cruz UFRN
  • Márcio Kreutz UFRN
  • Monica Pereira UFRN

Resumo


In conventional NoCs, it is common to use deterministic routing algorithms, which defines a unique route for communication between two processing cores and are implemented in hardware on the routers modules. However, the problem with having only one possible route between source and destination is the lack of alternative paths in case there is congestion or even obstructions along the route. A more recent approach to cope with this problem is the use of another NoCs paradigm which the routing algorithms are implemented in software, the Software-Defined Networks-on-Chip (SDNoCs). In this approach, the routing algorithm is executed by a core manager which creates and destroys virtual circuits to provide the communication between other cores, allowing the use of adaptive routing algorithms, which avoids deadlocks and provides more flexibility in creating the routes. The present work describes the proposal and implementation of a SDNoC, also presenting an investigation on its behavior when the traffics message exchange increases. Furthermore, the communication latency was evaluated over a deterministic and an adaptive routing algorithms. Finally, the experimental results the adaptive algorithm achieved better communication performance for a set of task graphs, reaching up to 3.6x of speedup comparing to the deterministic approach.

Palavras-chave: Multiprocessor/Multicore/Manycore Systems

Referências

W. Wolf A. A. Jerraya G. Martin "Multiprocessor system-on-chip (mpsoc) technology" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems vol. 27 no. 10 pp. 1701-1713 2008.

C. A. Zeferino A. A. Susin "Socin: a parametric and scalable network-on-chip" Integrated Circuits and Systems Design 2003. SBCCI 2003. Proceedings. 16th Symposium on pp. 169-174 2003.

R. Parikh V. Bertacco "Formally enhanced runtime verification to ensure noc functional correctness" Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture pp. 410-419 2011.

A. V. de Mello L. C. Ost F. G. Moraes N. L. V. Calazans "Evaluation of routing algorithms on mesh based nocs" PUCRS Av. Ipiranga pp. 22 2004.

A. Rashmi U. Pavitha "Efficient dynamic router architecture for optimized performance of noc systems" 2018 International Conference on Inventive Research in Computing Applications (ICIRCA) pp. 1062-1066 2018.

J. Hu R. Marculescu "Dyad: smart routing for networks-on-chip" Proceedings of the 41st annual Design Automation Conference pp. 260-263 2004.

K. Berestizshevsky G. Even Y. Fais J. Ostrometzky "Sdnoc: Software defined network on a chip" Microprocessors and Microsystems vol. 50 no. 10 pp. 138-153 2017.

E. W. Dijkstra "A note on two problems in connexion with graphs" Numerische mathematik vol. 1 no. 1 pp. 269-271 1959.

Systemc 2019 [online] Available: http://www.accellera.org/downloads/standards/systemc.

R. Manevich I. Cidon A. Kolodny S. Wimer et al. "Digital system design (dsd) 2011 14th euromicro conference on" Circuits and Systems (ISCAS) 2018 IEEE International Symposium on pp. 39-49 2011.

M. Ruaro H. M. Medina A. M. Amory F. G. Moraes "Softwaredefined networking architecture for noc-based many-cores" Circuits and Systems (ISCAS) 2018 IEEE International Symposium on pp. 1-5 2018.

L. Cong W. Wen W. Zhiying "A configurable programmable and software-defined network on chip" 2014 IEEE Workshop on Advanced Research and Technology in Industry Applications (WARTIA) pp. 813-816 2014.

N. McKeown T. Anderson H. Balakrishnan G. Parulkar L. Peterson J. Rexford S. Shenker J. Turner "Openflow: enabling innovation in campus networks" ACM SIGCOMM Computer Communication Review vol. 38 no. 2 pp. 69-74 2008.

V. Catania A. Mineo S. Monteleone M. Palesi D. Patti "Noxim: An open extensible and cycle-accurate network on chip simulator" 2015 IEEE 26th International Conference on Application-specific Systems Architectures and Processors (ASAP) pp. 162-163 2015.

R. Sandoval-Arechiga R. Parra-Michel J. Vazquez-Avila J. Flores-Troncoso S. Ibarra-Delgado "Software defined networks-on-chip for multi/many-core systems: A performance evaluation" Proceedings of the 2016 Symposium on Architectures for Networking and Communications Systems pp. 129-130 2016.

E. A. Carara Uma exploração arquitetural de redes intra-chip com topologia malha e modo de chaveamento wormhole 2004.

W. J. Dally "Virtual-channel flow control" ISCA ‘90 Proceedings of the 17th annual international symposium on Computer Architecture pp. 60-68 1990.

M. Goldbarg E. Goldbarg Grafos: Conceitos algoritmos e aplicações Elsevier pp. 185-292 2012.

C. A. Zeferino A. A. Susin "Socin: a parametric and scalable network-on-chip" Integrated Circuits and Systems Design 2003. SBCCI 2003. Proceedings. 16th Symposium on pp. 169-174 2003.

R. P. Dick D. L. Rhodes W. Wolf "Tgff: task graphs for free" Proceedings of the Sixth International Workshop on Hardware/Software Codesign.(CODES/CASHE’98) pp. 97-101 1998.

S. Tosun O. Ozturk E. Ozkan M. Ozen "Application mapping algorithms for mesh-based network-on-chip architectures" The Journal of Supercomputing vol. 71 no. 3 pp. 995-1017 2015.
Publicado
19/11/2019
SILVA, Raul Silveira; CRUZ , Patricia; KREUTZ, Márcio; PEREIRA, Monica. Communication Latency Evaluation on a Software-Defined Network-on-Chip. In: SIMPÓSIO BRASILEIRO DE ENGENHARIA DE SISTEMAS COMPUTACIONAIS (SBESC), 9. , 2019, Natal. Anais [...]. Porto Alegre: Sociedade Brasileira de Computação, 2019 . p. 41-48. ISSN 2237-5430.