Generation of Application Specific Fault Tolerant Irregular NoC Topologies Using Tabu Search
Initial Network on Chip (NoCs) topologies tended to have a regular structure, aiming flexibility regular performance for different applications, and multiple paths between routers. However, regular topologies lack in performance if compared to specific application generated topologies, often irregular. On the other hand, irregular topologies may lack flexibility (multiple communication paths). Moreover, in the billion-transistor era, circuit components are more susceptible to faults, transients and permanents. Due to the cost of producing such circuits, it is desirable to increase their lifespan which may be achieved by adding fault tolerance to the circuit, such as through hardware redundancy. This work proposes the generation of irregular topologies considering additional links to provide fault tolerance. The irregular topology with the additional links were generated through a Tabu Search approach. Thus generating intermediate topologies: flexible if compared to most irregular ones (some fault resistance), yet achieving application specific high performance if compared to regular NoCs.
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