Formal Verification of UML Sequence Diagrams in the Embedded Systems Context

  • E. Cunha UFAM
  • M. Custodio UFAM
  • H. Rocha UFAM
  • R. Barreto UFAM

Resumo


This paper shows a method for translating UML sequence diagrams to Petri nets and verifying deadlockfreeness, reachability, safety and liveness properties by using a model checker. In this proposed method, the user has not to know about temporal logics to describe the property to be verified. Instead, the user may adopt a high-level properties specification interface, which is automatically translated to a suitable temporal logic. We show the application of the proposed method in an embedded control application that consists of a sensory device mounted on a motorized platform that must detect and track specific objects in the environment.

Referências

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Publicado
07/11/2011
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CUNHA, E.; CUSTODIO, M.; ROCHA, H.; BARRETO, R.. Formal Verification of UML Sequence Diagrams in the Embedded Systems Context. In: SIMPÓSIO BRASILEIRO DE ENGENHARIA DE SISTEMAS COMPUTACIONAIS (SBESC), 1. , 2011, Florianópolis. Anais [...]. Porto Alegre: Sociedade Brasileira de Computação, 2011 . p. 39-45. ISSN 2237-5430.