DDR SDRAM Memory Controller for Digital TV Decoders
Resumo
This paper presents a multichannel DDR SDRAM memory controller to be used as an IP in a set-top box compliant with Brazilian Digital Television System. A set-top box is comprised by modules that access an external memory sharing the same bus. Thus, it is necessary a multichannel memory controller to schedule accesses. This work shows that the implemented system running at 100 MHz can achieve the necessary bandwidth to decode and exhibit HD 1080p resolution videos at 30 frames per second.
Referências
P. V. Wolf T. Henriksson. "Video processing requirements on SoC infrastructures " In Proceedings of the Conference on Design Automation and Test in Europe. DATE '08. ACM New York NY pp.1124-1125 2008.
JEDEC JESD79: Double data rate (DDR) SDRAM specification JEDEC Solid State Technology Association Virginia USA 2003.
BONATTO A. C. ; SOARES A. B. ; SUSIN A. A. . High Efficiency Reference Frames Storage for H.264/AVC Decoder Hardware Implementation. In: IEEE Latin American Symposium on Circuits and Systems 2010 Iguaçu Falls Brazil. IEEE Latin American Symposium on Circuits and Systems 2010. p. 304-307.
L. V. Agostini A. P. A. Filho W. T. Staehler V. S. Rosa B. Zatt A. C. M. Pinto R. E. Porto S. Bampi1 and A. A. Susin "Design and FPGA prototyping of a H.264/AVC main profile decoder for HDTV " Journal of the Brazilian Computer Society vol. 12 pp. 25-36 2007.
B. Zatt A. Azevedo L. Agostini A. Susin S. "Memory hierarchy targeting bi- predictive compensation for H.264/AVC decoder " VLSI 2007. '07. IEEE Computer Society Annual Symposium on 446 2007. Bampi. motion ISVLSI pp.445
A. C. Bonatto A. B. Soares A. A. Susin. "DDR SDRAM controller IP designed for reuse " In: IP Based Electronic System Conference & Exhibition - IP 08 France. Design and Reuse pp. 175-180 2008.
R. Wang J. Li C. Huang. "Motion compensation memory access optimization strategies for H.264/AVC decoder " Acoustics Speech and Signal Processing 2005. Proceedings. (ICASSP '05). IEEE International Conference on vol.5 pp. v97-v100 2005. (Pubitemid 43762352)
ITU-T Recommendation H.264 - Advanced video coding for generic audiovisual services Video Coding Experts Group Mar. 2005
JEDEC JESD79: Double data rate (DDR) SDRAM specification JEDEC Solid State Technology Association Virginia USA 2003.
BONATTO A. C. ; SOARES A. B. ; SUSIN A. A. . High Efficiency Reference Frames Storage for H.264/AVC Decoder Hardware Implementation. In: IEEE Latin American Symposium on Circuits and Systems 2010 Iguaçu Falls Brazil. IEEE Latin American Symposium on Circuits and Systems 2010. p. 304-307.
L. V. Agostini A. P. A. Filho W. T. Staehler V. S. Rosa B. Zatt A. C. M. Pinto R. E. Porto S. Bampi1 and A. A. Susin "Design and FPGA prototyping of a H.264/AVC main profile decoder for HDTV " Journal of the Brazilian Computer Society vol. 12 pp. 25-36 2007.
B. Zatt A. Azevedo L. Agostini A. Susin S. "Memory hierarchy targeting bi- predictive compensation for H.264/AVC decoder " VLSI 2007. '07. IEEE Computer Society Annual Symposium on 446 2007. Bampi. motion ISVLSI pp.445
A. C. Bonatto A. B. Soares A. A. Susin. "DDR SDRAM controller IP designed for reuse " In: IP Based Electronic System Conference & Exhibition - IP 08 France. Design and Reuse pp. 175-180 2008.
R. Wang J. Li C. Huang. "Motion compensation memory access optimization strategies for H.264/AVC decoder " Acoustics Speech and Signal Processing 2005. Proceedings. (ICASSP '05). IEEE International Conference on vol.5 pp. v97-v100 2005. (Pubitemid 43762352)
ITU-T Recommendation H.264 - Advanced video coding for generic audiovisual services Video Coding Experts Group Mar. 2005
Publicado
07/11/2011
Como Citar
SIQUEIRA, Hadley; SILVA, Ivan; KREUTZ, Marcio; CORREA, Edgard.
DDR SDRAM Memory Controller for Digital TV Decoders. In: SIMPÓSIO BRASILEIRO DE ENGENHARIA DE SISTEMAS COMPUTACIONAIS (SBESC), 1. , 2011, Florianópolis.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
2011
.
p. 78-82.
ISSN 2237-5430.
