Parallelism Level Analysis of Binary Field Multiplication on FPGAs

• Luckas A. Farias USP
• Bruno C. Albertini USP
• Paulo S. L. M. Barreto USP

Resumo

This work describes a pipelined architecture targeting FPGA binary field multiplication. It comprises a generic real time crypto coprocessor able to operate over any field, without a specific vendor specific technology. A performance comparison of this synthesized coprocessor is presented for two major FPGA vendors. The results show that the parallelism levels, often applied as a key point for decision-making, do not affect the area and power consumption in a linear manner, instead, present the local optimal points tied to the technology adopted for deployment.

Palavras-chave: Parallel processing, Field programmable gate arrays, Elliptic curve cryptography, Hardware, Galois fields, Parallel architectures, Cryptography, Elliptic Curve Cryptography, Binary Field, Binary Field Multiplication, FPGA, Architecture