CEVERO: A soft-error hardened SoC for aerospace applications
Resumo
Radiation in the space environment poses a constant threat to circuit devices, and, as a solution, several fault tolerance techniques have been developed. However, some techniques use either proprietary technology or radiation-hardening specialized foundries to manufacture, either of which are not easily accessible to most researchers. There is, yet, another set of rad-hard techniques which provide sufficient fault tolerance to specific aerospace applications. The CEVERO SoC is a custom proofof-concept design that implements techniques as lockstep, dual module redundancy and state recovery in its inner fault tolerance module. It is meant to integrate with the open-source PULP platform and to open a path to a full fault-tolerant SoC.
Palavras-chave:
Radiation-Hardened, Fault tolerance, Soft error, lockstep, DMR, CEVERO
Referências
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B. Schroeder, E. Pinheiro, and W. D. Weber, “DRAM errors in the wild: A large-scale field study,” Communications of the ACM, vol. 54, no. 2,pp. 100–107, 2011.
R. W. Berger, D. Bayles, R. Brown, S. Doyle, A. Kazemzadeh,K. Knowles, D. Moser, J. Rodgers, B. Saari, and D. Stanley, “The RAD750™ - A radiation hardened PowerPc™ processor for highperformance spaceborne applications,” in IEEE Aerospace Conference Proceedings, vol. 5. IEEE, 2001, pp. 52 263–52 272. [Online]. Available: http://ieeexplore.ieee.org/document/931184/
M. Iacoponi, “The RH-3000 MIPS compatible space processor,” in 9th Computing in Aerospace Conference, 1993, pp. 1–6.
X. Iturbe, B. Venu, E. Ozer, J. L. Poupat, G. Gimenez, and H. U. Zurek, “The Arm triple core lock-step (TCLS) processor,” ACM Transactionson Computer Systems, vol. 36, no. 3, 2019.
D. Rossi, F. Conti, A. Marongiu, A. Pullini, I. Loi, M. Gautschi, G. Tagliavini, A. Capotondi, P. Flatresse, and L. Benini, “PULP: A parallel ultra low power platform for next generation IoT applications,” 2015 IEEE Hot Chips 27 Symposium, HCS 2015, 2016.
D. Rossi, A. Pullini, I. Loi, M. Gautschi, F. K. Gurkaynak, A. Teman,J. Constantin, A. Burg, I. Miro-Panades, E. Beigne, F. Clermidy, P. Flatresse, and L. Benini, “Energy-Efficient Near-Threshold ParallelComputing: The PULPv2 Cluster,”IEEE Micro, vol. 37, no. 5, pp. 20–31, 2017.
P. D. Schiavone, F. Conti, D. Rossi, M. Gautschi, A. Pullini, E. Flamand,and L. Benini, “Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for internet-of-things applications,” 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2017, vol. 2017-Janua, pp. 1–8, 2017.
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J. F. Ziegler, “Terrestrial cosmic rays,” IBM Journal of Research and Development, vol. 40, no. 1, pp. 19–39, 1996.
D. Binder, E. C. Smith, and A. B. Holman, “Satellite Anomalies from Galactic Cosmic Rays,” IEEE Transactions on Nuclear Science, vol. 22, no. 6, pp. 2675–2680, 1975. [Online]. Available:http://ieeexplore.ieee.org/document/4328188/
J. C. Pickel and J. T. Blandford, “Cosmic ray induced errors in MOSmemory cells,” IEEE Transactions on Nuclear Science, vol. 25, no. 6,pp. 1166–1171, 1978.
C. S. Guenzer, E. A. Wolicki, and R. G. Alias, “Single event upset ofdynamic rams by neutrons and protons,” IEEE Transactions on Nuclear Science, vol. 26, no. 6, pp. 5048–5052, 1979.
A. Keys, J. Adams, D. Frazier, M. Patrick, M. Watson, M. Johnson,J. Cressler, and E. Kolawa, “Developments in Radiation-Hardened Electronics Applicable to the Vision for Space Exploration,” in AIAA SPACE 2007 Conference & Exposition. Reston, Virigina: American Institute of Aeronautics and Astronautics, sep 2007, pp. 1–10. [Online]. Available: http://arc.aiaa.org/doi/10.2514/6.2007-6269
S. S. Mukherjee, J. Emer, T. Fossum, and S. K. Reinhardt, “Cachescrubbing in microprocessors: Myth or necessity?” Proceedings - IEEE Pacific Rim International Symposium on Dependable Computing, pp.37–42, 2004.
B. Schroeder, E. Pinheiro, and W. D. Weber, “DRAM errors in the wild: A large-scale field study,” Communications of the ACM, vol. 54, no. 2,pp. 100–107, 2011.
R. W. Berger, D. Bayles, R. Brown, S. Doyle, A. Kazemzadeh,K. Knowles, D. Moser, J. Rodgers, B. Saari, and D. Stanley, “The RAD750™ - A radiation hardened PowerPc™ processor for highperformance spaceborne applications,” in IEEE Aerospace Conference Proceedings, vol. 5. IEEE, 2001, pp. 52 263–52 272. [Online]. Available: http://ieeexplore.ieee.org/document/931184/
M. Iacoponi, “The RH-3000 MIPS compatible space processor,” in 9th Computing in Aerospace Conference, 1993, pp. 1–6.
X. Iturbe, B. Venu, E. Ozer, J. L. Poupat, G. Gimenez, and H. U. Zurek, “The Arm triple core lock-step (TCLS) processor,” ACM Transactionson Computer Systems, vol. 36, no. 3, 2019.
D. Rossi, F. Conti, A. Marongiu, A. Pullini, I. Loi, M. Gautschi, G. Tagliavini, A. Capotondi, P. Flatresse, and L. Benini, “PULP: A parallel ultra low power platform for next generation IoT applications,” 2015 IEEE Hot Chips 27 Symposium, HCS 2015, 2016.
D. Rossi, A. Pullini, I. Loi, M. Gautschi, F. K. Gurkaynak, A. Teman,J. Constantin, A. Burg, I. Miro-Panades, E. Beigne, F. Clermidy, P. Flatresse, and L. Benini, “Energy-Efficient Near-Threshold ParallelComputing: The PULPv2 Cluster,”IEEE Micro, vol. 37, no. 5, pp. 20–31, 2017.
P. D. Schiavone, F. Conti, D. Rossi, M. Gautschi, A. Pullini, E. Flamand,and L. Benini, “Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for internet-of-things applications,” 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2017, vol. 2017-Janua, pp. 1–8, 2017.
“Ripes,” 2018. [Online]. Available: https://github.com/mortbopet/Ripes
Publicado
23/11/2020
Como Citar
SILVA, Igor; DO ESPÍRITO SANTO, Otávio; DO NASCIMENTO, Diego; XAVIER-DE-SOUZA, Samuel.
CEVERO: A soft-error hardened SoC for aerospace applications. In: TRABALHOS EM ANDAMENTO - SIMPÓSIO BRASILEIRO DE ENGENHARIA DE SISTEMAS COMPUTACIONAIS (SBESC), 10. , 2020, Evento Online.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
2020
.
p. 121-126.
ISSN 2763-9002.
DOI: https://doi.org/10.5753/sbesc_estendido.2020.13100.
