Architectural Exploration of an FPGA-based Hardware Accelerator for the Gaussian Filter using Approximate Computing

Resumo


The growing use of computer vision applications has increased the demand for efficient image processing implementations. These applications have constraints that, in some cases, can only be met by dedicated hardware implementations. This work presents architectures that apply approximate computing techniques to improve efficiency and scalability for implementing digital image filters on FPGA. These architectures were implemented as hardware accelerators for an embedded processor in an FPGA-based System-on-Chip. The results show that the use of approximate computing techniques can reduce costs without affecting results for the target application, which is an essential feature for further acceleration using parallel processing on hardware.

Palavras-chave: Image Processing, Computer Vision, Approximate Computing, Hardware Accelerator, FPGA

Referências

J. Redmon et al., “You only look once: Unified, real-time object detection,” in Proc. of the IEEE Conf. on Computer Vision and Pattern Recognition, 2016, pp. 779–788.

A. Filippeschi et al., “Survey of motion tracking methods based on inertial sensors: A focus on upper limb human motion,” Sensors, vol. 17, no. 6, p. 1257, 2017.

J. Long, E. Shelhamer, and T. Darrell, “Fully convolutional networks for semantic segmentation,” in Proc. of the IEEE Conf. on Computer Vision and Pattern Recognition, 2015, pp. 3431–3440.

M. Dossis, “High level synthesis for embedded systems,” in Embedded Systems: Theory and Design Methodology, K. Tanaka, Ed. BoD, 2012, ch. 16, pp. 341–266.

F. Vahid, Digital design with RTL design, VHDL, and Verilog. John Wiley & Sons, 2010.

F. Cabello et al., “Implementation of a fixed-point 2D Gaussian filter for image processing based on FPGA,” in 2015 Signal Processing: Algorithms, Architectures, Arrangements, and Applications (SPA). IEEE, 2015, pp. 28–33.

S. Mittal, “A survey of techniques for approximate computing,” ACM Comput Surv, vol. 48, no. 4, p. 62, 2016.

T. Li et al., “Efficient parallel implementation of morphological operation on GPU and FPGA,” in Proc. of the IEEE Int. Conf. on Security, Pattern Analysis, and Cybernetics (SPAC). IEEE, 2014, pp. 430–435.

D. G. Bailey, Design for embedded image processing on FPGAs. John Wiley & Sons, 2011.

R. Menaka, S. Janarthanan, and K. Deeba, “FPGA implementation of low power and high speed image edge detection algorithm,” Microprocess Microsyst, pp. 103053–1–103053–7, 2020.

D. Sangeetha and P. Deepa, “Fpga implementation of cost-effective robust Canny edge detection algorithm,” J Real Time Image Process, vol. 16, no. 4, pp. 957–970, 2019.

Z. Xiangxi et al., “FPGA implementation of edge detection for sobel operator in eight directions,” in IEEE Asia Pacific Conf. on Circuits and Systems (APCCAS). IEEE, 2018, pp. 520–523.

C. Solomon and T. Breckon, Fundamentals of Digital Image Processing: A practical approach with examples in Matlab. John Wiley & Sons, 2011.

R. Szeliski, Computer Vision – Algorithms and Applications, ser. Texts in Computer Science. Springer, 2011.

A. Joginipelly et al., “Efficient FPGA implementation of steerable Gaussian smoothers,” in Proc. of the 2012 44th Southeastern Symp. on System Theory (SSST). IEEE, 2012, pp. 78–82.

D. Salomon, Data compression: the complete reference. Springer, 2004.
Publicado
23/11/2020
Como Citar

Selecione um Formato
SBORZ, Guilherme; VIEL, Felipe; ZEFERINO, Cesar. Architectural Exploration of an FPGA-based Hardware Accelerator for the Gaussian Filter using Approximate Computing. In: TRABALHOS EM ANDAMENTO - SIMPÓSIO BRASILEIRO DE ENGENHARIA DE SISTEMAS COMPUTACIONAIS (SBESC), 10. , 2020, Evento Online. Anais [...]. Porto Alegre: Sociedade Brasileira de Computação, 2020 . p. 186-191. ISSN 2763-9002. DOI: https://doi.org/10.5753/sbesc_estendido.2020.13111.