A Partially Shared Thin Reconfigurable Array For Multicore Processor

  • Francisco Carlos Silva Junior UFPI
  • Ivan Silva UFPI
  • Ricardo Jacobi UnB


Reconfigurable architectures have been widely used as single core processor accelerators. In the multi-core era, however, it is necessary to review the way that reconfigurable arrays are integrated into multi-core processor. Generally, a set of reconfigurable functional units are employed in a similar way as they are used in single core processors. Unfortunately, a considerable increase in the area ensues from this practice. Besides, in applications with unbalanced workload in their threads this approach can lead to a inefficient use of the reconfigurable architecture in cores with a low or even idle workload. To cope with this issue, this work proposes and evaluates a partially shared thin reconfigurable array, which allows to share reconfigurable resources among the processor's cores. Sharing is performed dynamically by the configuration scheduler hardware. The results shows that the sharing mechanism provided 76% of energy savings, improving the performance 41% in average when compared with a version without the proposed reconfigurable array. A comparison with a version of the reconfigurable array without the sharing mechanism was performed and shows that the sharing mechanism improved up to 11.16% in the system performance.


R. Hameed, W. Qadeer, M. Wachs, O. Azizi, A. Solomatnikov, B. C. Lee, S. Richardson, C. Kozyrakis, and M. Horowitz, “Understanding sources of inefficiency in general-purpose chips,” in Proceedings of the 37th Annual International Symposium on Computer Architecture, ser. ISCA ’10. New York, NY, USA: ACM, 2010, pp. 37–47.

J. D. Souza, L. Carro, M. B. Rutzig, and A. C. S. Beck, “Towards a dynamic and reconfigurable multicore heterogeneous system,” in 2014 Brazilian Symposium on Computing Systems Engineering, Nov 2014, pp. 73–78.

J. D. Souza, L. Carro, M. B. Rutzig, and A. C. S. Beck, “A reconfigurable heterogeneous multicore with a homogeneous isa,” in 2016 Design, Automation Test in Europe Conference Exhibition (DATE), March 2016, pp. 1598–1603.

Accellera, “Systemc language,” https://www.accellera.org/downloads/standards/systemc, 2016, accessed: 29/07/2019.

S. Li, J. H. Ahn, R. D. Strong, J. B. Brockman, D. M. Tullsen, and N. P. Jouppi, “Mcpat: An integrated power, area, and timing modeling framework for multicore and manycore architectures,” in 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Dec 2009, pp. 469–480.

S. Hauck, T. W. Fry, M. M. Hosler, and J. P. Kao, “The chimaera reconfigurable functional unit,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 2, pp. 206–217, Feb 2004.

H. Singh, Ming-Hau Lee, Guangming Lu, F. J. Kurdahi, N. Bagherzadeh, and E. M. Chaves Filho, “Morphosys: an integrated reconfigurable system for data-parallel and computation-intensive applications,” IEEE Transactions on Computers, vol. 49, no. 5, pp. 465–481, May 2000.

S. C. Goldstein, H. Schmit, M. Budiu, S. Cadambi, M. Moe, and R. R. Taylor, “Piperench: a reconfigurable architecture and compiler,” Computer, vol. 33, no. 4, pp. 70–77, April 2000.

M. Wijtvliet, L. Waeijen, and H. Corporaal, “Coarse grained reconfigurable architectures in the past 25 years: Overview and classification,” in 2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), July 2016, pp. 235–244.

R. Hartenstein, “A decade of reconfigurable computing: A visionary retrospective,” in Proceedings of the Conference on Design, Automation and Test in Europe, ser. DATE ’01. Piscataway, NJ, USA: IEEE Press, 2001, pp. 642–649.

D. B. Gottlieb, J. J. Cook, J. D. Walstrom, S. Ferrera, Chi-Wei Wang, and N. P. Carter, “Clustered programmable-reconfigurable processors,” in 2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings., Dec 2002, pp. 134–141.

M. Shafique, L. Bauer, W. Ahmed, and J. Henkel, “Minority-game-based resource allocation for run-time reconfigurable multi-core processors,” in 2011 Design, Automation Test in Europe, March 2011, pp. 1–6.

A. C. S. Beck, M. B. Rutzig, G. Gaydadjiev, and L. Carro, “Transparent reconfigurable acceleration for heterogeneous embedded applications,” in 2008 Design, Automation and Test in Europe, March 2008, pp. 1208–1213.

M. A. Watkins, M. J. Cianchetti, and D. H. Albonesi, “Shared reconfigurable architectures for cmps,” in 2008 International Conference on Field Programmable Logic and Applications, Sep. 2008, pp. 299–304.

M. A. Watkins and D. H. Albonesi, “Remap: A reconfigurable heterogeneous multicore architecture,” in 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, Dec 2010, pp. 497–508.

L. Chen and T. Mitra, “Shared reconfigurable fabric for multi-core customization,” in 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC), June 2011, pp. 830–835.

L. Chen, T. Marconi, and T. Mitra, “Online scheduling for multi-core shared reconfigurable fabric,” in 2012 Design, Automation Test in Europe Conference Exhibition (DATE), March 2012, pp. 582–585.

P. Garcia and K. Compton, “Kernel sharing on reconfigurable multiprocessor systems,” in 2008 International Conference on Field-Programmable Technology, Dec 2008, pp. 225–232.

D. A. Patterson and J. L. Henessy, Computer Architecture: A Quantitative Approach, 5th ed. Oxford, USA: Morgan Kaufmann, 2016.

L. Lamport, “How to make a multiprocessor computer that correctly executes multiprocess programs,” IEEE Transactions on Computers, vol. C-28, no. 9, pp. 690–691, Sep. 1979.

M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown, “Mibench: A free, commercially representative embedded benchmark suite,” in Proceedings of the Fourth Annual IEEE International Workshop on Workload Characterization. WWC-4 (Cat. No.01EX538), Dec 2001, pp. 3–14.

A. J. Dorta, C. Rodriguez, and F. de Sande, “The openmp source code repository,” in 13th Euromicro Conference on Parallel, Distributed and Network-Based Processing, Feb 2005, pp. 244–250.
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SILVA JUNIOR, Francisco Carlos; SILVA, Ivan; JACOBI, Ricardo. A Partially Shared Thin Reconfigurable Array For Multicore Processor. In: TRABALHOS EM ANDAMENTO - SIMPÓSIO BRASILEIRO DE ENGENHARIA DE SISTEMAS COMPUTACIONAIS (SBESC), 9. , 2019, Natal. Anais [...]. Porto Alegre: Sociedade Brasileira de Computação, 2019 . p. 113-118. ISSN 2763-9002. DOI: https://doi.org/10.5753/sbesc_estendido.2019.8645.