Calibração de Latência Microarquitetural: Uma Abordagem Baseada em Serialização de Instruções e Compensação de Drift

• Matheus B. Guerra UFRJ
• José L. N. C. de Oliveira UFRJ https://orcid.org/0009-0001-2202-9037
• Diego L. C. Dutra UFRJ https://orcid.org/0000-0003-4262-7242

DOI: https://doi.org/10.5753/sbseg.2026.26916

Resumo

Este trabalho apresenta uma metodologia para calibração automática de latências de cache, eliminando ajustes manuais e empíricos em ataques de canal lateral. A abordagem utiliza instruções de serialização e o Time Stamp Counter (TSC) para garantir medições precisas no espaço de usuário. O diferencial reside no isolamento sistemático dos níveis de cache e na compensação de data drift frente a flutuações de frequência da CPU. Resultados em hardware moderno confirmam a eficácia do método ao atingir conformidade com os valores encontrados da literatura.

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