Improving Traceability and Collaboration in HDL Design with GitFlow and CI Pipelines

• Renan Carlos Gomes de Farias UFSM https://orcid.org/0009-0002-7147-9357
• João Pedro Buzatti Mendes UFSM https://orcid.org/0009-0000-9001-7436
• Lisandra Manzoni Fontoura UFSM https://orcid.org/0000-0002-4669-1383
• Mateus Beck Rutzig UFSM https://orcid.org/0000-0002-2836-2009

DOI: https://doi.org/10.5753/semish.2026.21853

Resumo

The complexity of digital hardware design has been increasing with the scale of CMOS technology. Thus, front-end design and verification teams face demands for modularity and traceability to shrink tape-out time and avoid failures on functional verification process. However, the employment of non-standard practices of project management in HDL-based workflows have long been spread in the microelectronics community. This work proposes a version control and continuous integration pipeline methodologies based on Gitflow aiming to improve collaboration between front-end and verification teams focusing on ASIC designs. By employing such an approach in a blueMacaw Microcontroller project, which resulted in a 22 nm tape-out, we achieved a highly effective workflow that ensured early error detection, traceability and strong team integration.

Palavras-chave: GitFlow, HDL design, ASIC front-end, version control, continuous integration

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