Exploração de Desempenho, Consumo Dinâmico e Eficiência Energética em MPSoCs
Resumo
Para realizar exploração de desempenho e eficiência energética em projetos de MPSoCs, faz-se necessária uma infraestrutura de simulação em nível de sistema que forneça recursos para avaliar consumo de energia nos estágios iniciais do projeto. Este artigo apresenta uma extensão de um framework para projetos MPSoCs que fornece suporte à escalabilidade dinâmica de voltagem e frequência (DVFS) em simuladores de MPSoCs e a avalia três mecanismos de DVFS. Os experimentos mostram que a aplicação de técnicas de DVFS pode economizar energia consideravelmente, com insignificante perda de desempenho da simulação.
Referências
Azevedo, R., Rigo, S., Bartholomeu, M., Araujo, G., Araujo, C., and Barros, E. (2005). The ArchC Architecture Description Language and Tools. In International Journal of Parallel Programming. Vol. 33, No. 5, pages 453–484.
Binkert, N., Beckmann, B., Black, G., Reinhardt, S. K., Saidi, A., Basu, A., Hestness, J., Hower, D. R., Krishna, T., Sardashti, S., Sen, R., Sewell, K., Shoaib, M., Vaish, N., Hill, M. D., and Wood, D. A. (2011). The gem5 simulator. volume 39, pages 1–7.
Brooks, D., Tiwari, V., and Martonosi, M. (2000). Wattch: A framework for architecturallevel power analysis and optimizations. SIGARCH Comput. Archit. News, 28(2):83–94.
Duenha, L., Guedes, M., Almeida, H., Boy, M., and Azevedo, R. (2014). Mpsocbench: A toolset for mpsoc system level evaluation. In Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), INSPEC Number: 14564763, pages 164–171. IEEE.
Guedes, M., Auler, R., Duenha, L., Borin, E., and Azevedo, R. (2013). An automatic energy consumption characterization of processors using archc. Journal of Systems Architecture, 59(8):603 – 614.
III, J. H. L., Pedretti, K., Kelly, S. M., Shu, W., abd, K. F., Dyke, J. V., and Vaughan, C. (2012). Energy-Efcient High Performance Computing: Measurement and Tuning. Springer New York.
Kong, J., Choi, J., Choi, L., and Chung, S. W. (Nov-2008). Low-cost application-aware dvfs for multi-core architecture. In Proceedings of 3rd International Conference on Convergence and Hybrid Information Technology, volume 2 of ISBN:978-0-76953407-7, pages 106–111, Busan. IEEE.
Li, S., Ahn, J., and Strong, R. (2009). McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures. In Proceedings of the 42nd Annual International Symposium on Microarchitecture, pages 469–480.
Martins, A., Silva, D., Castilhos, G., Monteiro, T., and Moraes, F. (2014). A method for noc-based mpsoc energy consumption estimation. In International Conference on Electronics, Circuits and Systems (ICECS). IEEE.
Muralimanohar, N., Balasubramonian, R., and Jouppi, N. P. (2009). Cacti 6.0: A tool to model large caches. HP Laboratories, pages 22–31.
Rosenfeld, P., Cooper-Balis, E., and Jacob, B. (2011). Dramsim2: A cycle accurate memory system simulator. In IEEE-Computer Architecture Letters, ISSN 1556-6056, pages 16–19, Maryland, USA. IEEE.
Spiliopoulos, V., Bagdia, A., Hansson, A., Aldworth, P., and Kaxiras, S. (2013). Introducing dvfs-management in a full-system simulator. Proceedings of the IEEE 21st International Symposium on Modeling, Analysis & Simulation of Computer and Telecommunication Systems (MASCOTS-2013), pages 535–545.
Tiwari, V., Malik, S., and Wolfe, A. (1994). Power analysis of embedded software: A rst step towards software power minimization. In IEEE Transactions on VLSI Systems, vol. 2, page 437–445.
Weiser, M., Welch, B., Demers, A., and Shenker, S. (1994). Scheduling for reduced cpu energy. In Proceedings of the 1st USENIX Conference on Operating Systems Design and Implementation, OSDI '94, Berkeley, CA, USA. USENIX Association.
Yadav, M., Casu, M., and Zamboni, M. (Oct, 2013). Laura-noc: Local automatic rate adjustment in network-on-chips with a simple dvfs. In IEEE Transactions on Symposium on Circuits and Systems II: Express Briefs, volume 60 of ISSN:1549-7747, pages 647 – 651. IEEE.
Binkert, N., Beckmann, B., Black, G., Reinhardt, S. K., Saidi, A., Basu, A., Hestness, J., Hower, D. R., Krishna, T., Sardashti, S., Sen, R., Sewell, K., Shoaib, M., Vaish, N., Hill, M. D., and Wood, D. A. (2011). The gem5 simulator. volume 39, pages 1–7.
Brooks, D., Tiwari, V., and Martonosi, M. (2000). Wattch: A framework for architecturallevel power analysis and optimizations. SIGARCH Comput. Archit. News, 28(2):83–94.
Duenha, L., Guedes, M., Almeida, H., Boy, M., and Azevedo, R. (2014). Mpsocbench: A toolset for mpsoc system level evaluation. In Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), INSPEC Number: 14564763, pages 164–171. IEEE.
Guedes, M., Auler, R., Duenha, L., Borin, E., and Azevedo, R. (2013). An automatic energy consumption characterization of processors using archc. Journal of Systems Architecture, 59(8):603 – 614.
III, J. H. L., Pedretti, K., Kelly, S. M., Shu, W., abd, K. F., Dyke, J. V., and Vaughan, C. (2012). Energy-Efcient High Performance Computing: Measurement and Tuning. Springer New York.
Kong, J., Choi, J., Choi, L., and Chung, S. W. (Nov-2008). Low-cost application-aware dvfs for multi-core architecture. In Proceedings of 3rd International Conference on Convergence and Hybrid Information Technology, volume 2 of ISBN:978-0-76953407-7, pages 106–111, Busan. IEEE.
Li, S., Ahn, J., and Strong, R. (2009). McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures. In Proceedings of the 42nd Annual International Symposium on Microarchitecture, pages 469–480.
Martins, A., Silva, D., Castilhos, G., Monteiro, T., and Moraes, F. (2014). A method for noc-based mpsoc energy consumption estimation. In International Conference on Electronics, Circuits and Systems (ICECS). IEEE.
Muralimanohar, N., Balasubramonian, R., and Jouppi, N. P. (2009). Cacti 6.0: A tool to model large caches. HP Laboratories, pages 22–31.
Rosenfeld, P., Cooper-Balis, E., and Jacob, B. (2011). Dramsim2: A cycle accurate memory system simulator. In IEEE-Computer Architecture Letters, ISSN 1556-6056, pages 16–19, Maryland, USA. IEEE.
Spiliopoulos, V., Bagdia, A., Hansson, A., Aldworth, P., and Kaxiras, S. (2013). Introducing dvfs-management in a full-system simulator. Proceedings of the IEEE 21st International Symposium on Modeling, Analysis & Simulation of Computer and Telecommunication Systems (MASCOTS-2013), pages 535–545.
Tiwari, V., Malik, S., and Wolfe, A. (1994). Power analysis of embedded software: A rst step towards software power minimization. In IEEE Transactions on VLSI Systems, vol. 2, page 437–445.
Weiser, M., Welch, B., Demers, A., and Shenker, S. (1994). Scheduling for reduced cpu energy. In Proceedings of the 1st USENIX Conference on Operating Systems Design and Implementation, OSDI '94, Berkeley, CA, USA. USENIX Association.
Yadav, M., Casu, M., and Zamboni, M. (Oct, 2013). Laura-noc: Local automatic rate adjustment in network-on-chips with a simple dvfs. In IEEE Transactions on Symposium on Circuits and Systems II: Express Briefs, volume 60 of ISSN:1549-7747, pages 647 – 651. IEEE.
Publicado
18/10/2015
Como Citar
DUENHA, Liana; MADALOZZO, Guilherme; SANTIAGO, Thiago; MORAES, Fernando; AZEVEDO, Rodolfo.
Exploração de Desempenho, Consumo Dinâmico e Eficiência Energética em MPSoCs. In: SIMPÓSIO EM SISTEMAS COMPUTACIONAIS DE ALTO DESEMPENHO (SSCAD), 16. , 2015, Florianópolis.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
2015
.
p. 60-71.
DOI: https://doi.org/10.5753/wscad.2015.14272.
