Scratchpad Memories for Parallel Applications in Multi-core Architectures
Resumo
Scratchpad memories are largely used in embedded processors due to their reduced energy consumption and area compared to traditional cache memories. In multi-core architectures, these memories are an interesting solution for the storage of shared data and data which is used intensively. However, these memories present some challenges, such as the need for manual choice of the content. Furthermore, different sizes of scratchpad memories result in the need to modify the source code of the application. In this article, we propose the use of a scratchpad memory in a multi-core architecture which alleviates these disadvantages. We added the scratchpad to an architecture consisting of 4 cores, reducing the size of L2 cache in order to give chip area to the scratchpad memory. We evaluated our proposed design by executing the NAS Parallel Benchmark (NPB) applications in a simulator. We improved performance by up to 45% compared to the base architecture, reducing cache invalidations by up to 85%.
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