FPGA-based Accelerator to Speed-up Seismic Applications
Resumo
Hardware accelerators such as GPGPUs and FPGAs have been used as an alternative to the conventional CPU in scientific computing applications and have shown significant performance improvements. In this context, this work presents an FPGA-based solution that explores efficiently the reuse of data and parallelization in both space and time domains for the first computational stage of the RTM (Reverse Time Migration) algorithm, the seismic modeling. We also implemented the same algorithm for CPU architectures and GPGPU and our results demonstrate that the FPGA-based approach can be a viable solution to improve performance. Experimental results show a speedup of 1.668 times compared with GPGPU and 25.79 times compared to CPU. Results were evaluated with the Marmousi velocity model, considering the same parameters in all approaches.
Referências
R. G. Clapp, H. Fu, and O. Lindtjorn. "Selecting the right hardware for Reverse Time Migration". In: The Leading Edge 29: 48-58, January 2010.
Thomas, D.B.; Howes, L.; Luk, W. “A Comparison of CPUs, GPUs, FPGAs, and Massively Paralell Processor Arrays for Random Number Generation”. FPGA 2009, pp.63-72.
S. Che, J. Li, J.W. Sheaffer, K. Skadron, and J. Lach. "Accelerating Compute Intensive Applications with GPUs and FPGAs". In: Proc. Symp. Application Specific Processors, pp. 101-107, 2008.
M. B. Gokhale and P. S. Graham. "Reconfigurable computing: Accelerating computation with field-programmable gate arrays". Springer-Verlag, ISBN: 0387261052. New York, 2005.
C. He, G. Qin, M. Lu, W. Zhao. "Optimized high-order finite difference wave equations modeling on reconfigurable computing platform". In: Microprocessors & Microsystems, v. 31 , pp.103-115, March 2007.
S. Brown, “Performance Comparison of finite-difference modeling on Cell, FPGA and multi-core computers”, SEG, SEG Publisher, San Antonio, 2007, pp. 2110-2114.
W. W. Symes, \Reverse time migration with optimal checkpointing," Geo-physics, vol. 72, no. 5, pp. SM213-SM221, 2007. [Online]. Available: http://link.aip.org/link/?GPY/72/SM213/1
C. Petrie, C. Cump, M. Devlin, and K. Regester, "High performance embedded computing using Field Programmable Gate Arrays", In: Proceedings of the 8th Annual Workshop on High-Performance Embedded Computing, 2004, pp. 124-150.
H. Fu, W. Osborne, R. G. Clapp, O. Mencer and W. Luck. “Accelerating Seismic Computations Using Customized Number Representations of FPGAs” EURASIP Journal on Embedded Systems, vol. 2009, Article ID 382983, doi: 10;.1155/2009/382983, pp. 1–13, 2009.
C. Chang, J. Wawrzynek, and R. Brodersen, "Bee2: a high-end reconfigurable computing system," Design Test of Computers, IEEE, vol. 22, no. 2, pp. 114-125, mar. 2005.
Plataformas da GiDEL: PROCe III. Disponível em: http://www.gidel.com/PROCe%20III.htm. Acessado em Junho de 2011.
FPGA Stratix III da Altera. Disponível em: [link]. Acessado em Junho de 2011.
O. Yilmaz, Seismic Data Analysis. Tulsa, OK: Society of Exploration Geophysicists, 2001. [Online]. Available: http://link.aip.org/link/doi/10.1190/1.9781560801580.
FPGAs da Xilinx. Disponível em: http://www.xilinx.com. Acessado em: 22/06/2011.
GPGPU da NVidia. Disponível em: http://www.nvidia.com. Acessado em: 22/06/2011.
GPGPU Tesla T10. Disponível em: http://www.nvidia.cn/docs/IO/56483/Tesla_C1060_boardSpec_v03.pdf. Acessado em: 14/07/2011.
Trevor Irons. Marmousi Model. http://www.ahay.org/RSF/book/data/marmousi/paper.pdf. Consultado em: 18 de Julho de 2010.
