MPSoC Minimalista com Caches Coerentes Implementado num FPGA
Resumo
Este artigo descreve o projeto e a implementação de um MPSoC com caches coerentes num FPGA. O sistema pode ser compilado para conter de 1 a 8 processadores MIPS- I, caches de dados coerentes (L1), unidades de gerenciamento de memória, controladores de memória e um barramento multiplexado. O artigo contém uma descrição detalhada da implementação em VHDL, enfocando o sistema de memória. A inicialização do sistema e a sincronização com semáforos é discutida brevemente. Um programa de testes simples é usado para aferir, preliminarmente, o desempenho do sistema.Referências
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D. Culler, J. P. Singh, and A. Gupta. Parallel Computer Architecture: A Hardware/Software Approach. Morgan Kaufmann, 1998. ISBN 1-55860-343-3.
H. C. Freitas, F. R. Wagner, P. O. A. Navaux, and C. A. P. S. Martins. Projeto de um processador de rede intra-chip para controle de comunicação entre múltiplos cores. WSCAD’06: VII Workshop em Sistemas Computacionais de Alto Desempenho, págs 3–10, 2006.
GaislerResearch. http://www.gaisler.com, 2008.
R. Gindin, I. Cidon, and I. Keidar. NoC-Based FPGA: Architecture and routing. NOCS’07: 1st Intl Symp on Networks-on-Chip, págs 253–264. IEEE, 2007.
G. Gir˜ao, B. C. de Oliveira, R. Soares, and I. S. Silva. Cache coherency communication cost in a NoC-based MPSoC platform. SBCCI’07: 20th Conf on Integrated Circuits and Systems Design, págs 288–293. ACM, 2007.
J. R. Goodman. Using cache memory to reduce processor-memory traffic. ISCA’83: 10th Intl Symp on Computer Arch, págs 124–131, 1983.
J. L. Hennessy and D. A. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufmann, 4th edition, 2007. ISBN 0-12-370490-1.
M. Kreutz, C. A. Marcon, L. Carro, F.Wagner, and A. A. Susin. Design space exploration comparing homogeneous and heterogeneous network-on-chip architectures. SBCCI’05: 18th Conf on Integrated Circuits and Systems Design, págs 190–195, 2005.
M. Loghi, M. Poncino, and L. Benini. Cache coherence tradeoffs in shared memory MPSoCs. ACM Trans on Embedded Computer Systems, 5(2):383–407, 2006.
miniMIPS. https://www.opencores.org/?do=project\&who=minimips, 2009.
B. A. Nayfeh, L. Hammond, and K. Olukotun. Evaluation of design alternatives for a multiprocessor microprocessor. ISCA’96: 23rd Intl Symp on Computer Arch, págs 67–77, 1996.
B. A. Nayfeh and K. Olukotun. Exploring the design space for a shared-cache multiprocessor. ISCA’94: 21st Intl Symp on Computer Arch, págs 166–175, 1994.
K. Olukotun, B. A. Nayfeh, L. Hammond, K. Wilson, and K. Chang. The case for a single-chip multiprocessor. ASPLOS’94: 6th Intl Conf on Arch Support for Progr Lang and Oper Sys, págs 2–11, 1994.
OpenRisc1k. http://www.opencores.org/?do=project\&who=or1k, 2008.
M. S. Papamarcos and J. H. Patel. A low-overhead coherence solution for multiprocessors with private cache memories. ISCA’84: 11th Intl Symp on Computer Arch, págs 348–354, 1984.
P. Sweazey and A. J. Smith. A class of compatible cache consistency protocols and their support by the IEEE Futurebus. ISCA’86: 13th Intl Symp on Computer Arch, págs 414–423, 1986.
D. Sweetman. See MIPS Run – Linux. Morgan Kaufmann, 2nd edition, 2007. ISBN 0-12-088421-6.
D. Wingard. NoC is the answer! (what was the question?). MPSoC’06 presentations - 6th Intl Forum on Application- Specific Multi-Processor SoC. IEEE, 2006.
Xilinx. http://www.xilinx.com/microblaze, 2008.
Altera. http://www.altera.com/nios, 2008.
F. Baskett, T. A. Jermoluk, and D. Solomon. The 4D- MP graphics superworkstation: Computing + graphics = 40 MIPS + 40 MFLOPS and 100,000 lighted polygons per second. COMPCON, págs 468–471, 1988.
D. Culler, J. P. Singh, and A. Gupta. Parallel Computer Architecture: A Hardware/Software Approach. Morgan Kaufmann, 1998. ISBN 1-55860-343-3.
H. C. Freitas, F. R. Wagner, P. O. A. Navaux, and C. A. P. S. Martins. Projeto de um processador de rede intra-chip para controle de comunicação entre múltiplos cores. WSCAD’06: VII Workshop em Sistemas Computacionais de Alto Desempenho, págs 3–10, 2006.
GaislerResearch. http://www.gaisler.com, 2008.
R. Gindin, I. Cidon, and I. Keidar. NoC-Based FPGA: Architecture and routing. NOCS’07: 1st Intl Symp on Networks-on-Chip, págs 253–264. IEEE, 2007.
G. Gir˜ao, B. C. de Oliveira, R. Soares, and I. S. Silva. Cache coherency communication cost in a NoC-based MPSoC platform. SBCCI’07: 20th Conf on Integrated Circuits and Systems Design, págs 288–293. ACM, 2007.
J. R. Goodman. Using cache memory to reduce processor-memory traffic. ISCA’83: 10th Intl Symp on Computer Arch, págs 124–131, 1983.
J. L. Hennessy and D. A. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufmann, 4th edition, 2007. ISBN 0-12-370490-1.
M. Kreutz, C. A. Marcon, L. Carro, F.Wagner, and A. A. Susin. Design space exploration comparing homogeneous and heterogeneous network-on-chip architectures. SBCCI’05: 18th Conf on Integrated Circuits and Systems Design, págs 190–195, 2005.
M. Loghi, M. Poncino, and L. Benini. Cache coherence tradeoffs in shared memory MPSoCs. ACM Trans on Embedded Computer Systems, 5(2):383–407, 2006.
miniMIPS. https://www.opencores.org/?do=project\&who=minimips, 2009.
B. A. Nayfeh, L. Hammond, and K. Olukotun. Evaluation of design alternatives for a multiprocessor microprocessor. ISCA’96: 23rd Intl Symp on Computer Arch, págs 67–77, 1996.
B. A. Nayfeh and K. Olukotun. Exploring the design space for a shared-cache multiprocessor. ISCA’94: 21st Intl Symp on Computer Arch, págs 166–175, 1994.
K. Olukotun, B. A. Nayfeh, L. Hammond, K. Wilson, and K. Chang. The case for a single-chip multiprocessor. ASPLOS’94: 6th Intl Conf on Arch Support for Progr Lang and Oper Sys, págs 2–11, 1994.
OpenRisc1k. http://www.opencores.org/?do=project\&who=or1k, 2008.
M. S. Papamarcos and J. H. Patel. A low-overhead coherence solution for multiprocessors with private cache memories. ISCA’84: 11th Intl Symp on Computer Arch, págs 348–354, 1984.
P. Sweazey and A. J. Smith. A class of compatible cache consistency protocols and their support by the IEEE Futurebus. ISCA’86: 13th Intl Symp on Computer Arch, págs 414–423, 1986.
D. Sweetman. See MIPS Run – Linux. Morgan Kaufmann, 2nd edition, 2007. ISBN 0-12-088421-6.
D. Wingard. NoC is the answer! (what was the question?). MPSoC’06 presentations - 6th Intl Forum on Application- Specific Multi-Processor SoC. IEEE, 2006.
Xilinx. http://www.xilinx.com/microblaze, 2008.
Publicado
28/10/2009
Como Citar
TORTATO JR, Jorge; HEXSEL, Roberto A..
MPSoC Minimalista com Caches Coerentes Implementado num FPGA. In: SIMPÓSIO EM SISTEMAS COMPUTACIONAIS DE ALTO DESEMPENHO (SSCAD), 10. , 2009, São Paulo.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
2009
.
p. 103-110.
DOI: https://doi.org/10.5753/wscad.2009.17398.
