Técnica de Proteção de Bytecodes para Processador Java em Tecnologia CMOS
Resumo
O soft core JOP (Java Optimized Processor) para FPGAs (Field Programmable Gate Array) é uma implementação otimizada da máquina virtual Java em hardware, para aplicações de tempo real. No entanto, este processador não contempla em sua arquitetura técnicas de tolerância a falhas. O trabalho descrito neste artigo é parte de um esforço maior para tornar o processador JOP um processador tolerante a falhas. Neste artigo, apresentamos os resultados da aplicação de uma técnica de tolerância a falhas, proteção de memória através de ECC (Error Correction Code), no soft core JOP, que detecta e corrige erros na área destinada ao código da memória SRAM (Static Random Access Memory). A ocorrência da falha é percebida no nível sistêmico através de uma exceção, característica esta disponível na linguagem Java. Este artigo apresenta resultados inovadores na medida em que não existem registrados na literatura outro processador Java de tempo real e tolerante a falhas.Referências
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J. Gaisler. Concurrent error-detection and modular fault-tolerance in a 32-bit processing core for embedded space flight applications. In Fault-Tolerant Computing, 1994. FTCS-24. Digest of Papers., Twenty-Fourth International Symposium on, pages 128–130, June 1994.
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C. Meinhardt, R. Reis, M. Violante, and M. Reorda. Recovery scheme for hardening system on programmable chips. In Test Workshop, 2009. LATW ’09. 10th Latin American, pages 1–6, March 2009.
P. Mikhalenko. Real-time java: An introduction, September 2008.
C. R. Moratelli, E. Cota, and M. S. Lubaszewski. A cryptography core tolerant to dfa fault attacks. Journal Integrated Circuits and Systems, 2(1):14–21, 2007.
D. A. Patterson and J. L. Hennessy. Computer Organization and Design: The Hardware/Software Interface. Morgan Kaufmann, 3 edition, 2007.
W. Puffitsch and M. Schoeberl. picoJava-II in an FPGA. In Proceedings of the 5th 5th International Workshop on Java Technologies for Real-time and Embedded Systems (JTRES 2007), pages 213–221, Vienna, Austria, September 2007. ACM Press.
N. Quach. High availability and reliability in the itanium processor. IEEE Micro, 20(5):61–69, 2000.
M. Schoeberl. JOP: A Java Optimized Processor for Embedded Real-Time Systems. Phd thesis, Vienna University of Technology, 2005.
M. Schoeberl. Jop Reference Handbook. 1 edition, 2007.
M. Schoeberl. A Java processor architecture for embedded real-time systems. Journal of Systems Architecture, doi:10.1016/j.sysarc.2007.06.001, 2008.
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A. Burns and A. Wellings. Real-Time Systems and Their Programming Languages. Addison-Wesley, 1991.
H. Castro, A. A. Coelho, and R. J. Silveira. Fault-tolerance in fpga’s through crc voting. In SBCCI ’08: Proceedings of the 21st Annual Symposium on Integrated Circuits And System Design, pages 188–192, New York, NY, USA, 2008. ACM.
M. A. Check and T. J. Slegel. Custom s/390 g5 and g6 microprocessors. IBM J. RES. DEVELOP, 43(5/6):671–680, SEPTEMBER/NOVEMBER 1999.
H. de Sousa Castro. Fault Tolerance Through Reconfigurability: Applications In Space Instrumentation. Phd thesis, The University of Sussex, June 1992.
Érika Cota, F. Lima, S. Rezgui, L. Carro, R. Velazco, M. Lubaszewski, and R. Reis. Synthesis of an 8051-like micro-controller tolerant to transient faults. J. Electron. Test., 17(2):149–161, 2001.
J. Gaisler. Concurrent error-detection and modular fault-tolerance in a 32-bit processing core for embedded space flight applications. In Fault-Tolerant Computing, 1994. FTCS-24. Digest of Papers., Twenty-Fourth International Symposium on, pages 128–130, June 1994.
J. Gaisler. A portable and fault-tolerant microprocessor based on the sparc v8 architecture. In DSN ’02: Proceedings of the 2002 International Conference on Dependable Systems and Networks, pages 409–415, Washington, DC, USA, 2002. IEEE Computer Society.
T. R. Halfhill. Imsys hedges bets on Java. Microprocessor Report, pages 1–4, August 2000.
J. Kreuzinger, U. Brinkschulte, M. Pfeffer, S. Uhrig, and T. Ungerer. Real-time event-handling and scheduling on a multithreaded Java microcontroller. Microprocessors and Microsystems, 27(1):19–31, 2003.
C. Meinhardt, R. Reis, M. Violante, and M. Reorda. Recovery scheme for hardening system on programmable chips. In Test Workshop, 2009. LATW ’09. 10th Latin American, pages 1–6, March 2009.
P. Mikhalenko. Real-time java: An introduction, September 2008.
C. R. Moratelli, E. Cota, and M. S. Lubaszewski. A cryptography core tolerant to dfa fault attacks. Journal Integrated Circuits and Systems, 2(1):14–21, 2007.
D. A. Patterson and J. L. Hennessy. Computer Organization and Design: The Hardware/Software Interface. Morgan Kaufmann, 3 edition, 2007.
W. Puffitsch and M. Schoeberl. picoJava-II in an FPGA. In Proceedings of the 5th 5th International Workshop on Java Technologies for Real-time and Embedded Systems (JTRES 2007), pages 213–221, Vienna, Austria, September 2007. ACM Press.
N. Quach. High availability and reliability in the itanium processor. IEEE Micro, 20(5):61–69, 2000.
M. Schoeberl. JOP: A Java Optimized Processor for Embedded Real-Time Systems. Phd thesis, Vienna University of Technology, 2005.
M. Schoeberl. Jop Reference Handbook. 1 edition, 2007.
M. Schoeberl. A Java processor architecture for embedded real-time systems. Journal of Systems Architecture, doi:10.1016/j.sysarc.2007.06.001, 2008.
M. L. Shooman. Reliability of Computer Systems and Networks. Wiley, 1 edition, 2002.
A. S. Tanenbaum. Modern Operating Systems. Pearson Education, 3 edition, 2008.
Xilinx, Inc. Spartan-3 Starter Kit Board User Guide, May 2005. v1.2.
Publicado
28/10/2009
Como Citar
SILVEIRA, Jardel; VIANA, David; CASTRO, Helano; COELHO, Alexandre; SILVEIRA, Jarbas.
Técnica de Proteção de Bytecodes para Processador Java em Tecnologia CMOS. In: SIMPÓSIO EM SISTEMAS COMPUTACIONAIS DE ALTO DESEMPENHO (SSCAD), 10. , 2009, São Paulo.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
2009
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p. 161-165.
DOI: https://doi.org/10.5753/wscad.2009.17405.
