PowerSMT: Ferramenta para Análise de Consumo de Potência em Arquiteturas SMT
Resumo
As aplicações estão mais complexas, exigindo um processamento mais agressivo, tal como aquele obtido com as atuais arquiteturas SMT. Para avaliar o desempenho destas arquiteturas, ainda na fase de projeto, a ferramenta SS_SMT tem sido usada satisfatoriamente. Entretanto, como nestas arquiteturas as estruturas e os circuitos são maiores do que aqueles existentes nas arquiteturas superescalares convencionais, espera-se que o consumo de potência também seja maior. Nesse sentido, maiores estudos se fazem necessários para avaliar esta questão. Neste trabalho, a ferramenta SS_SMT foi adaptada para permitir a análise de consumo eficiente de potência, dando origem a nova ferramenta PowerSMT, a qual tem como base as plataformas SimpleScalar e CACTI. PowerSMT foi exaustivamente experimentada na análise da cache de instruções, estações de reserva e unidades funcionais. Os resultados sobre benchmarks do SPEC mostraram que a ferramenta é de fundamental importância na análise do consumo de potência em arquiteturas SMT.Referências
BROOKS, D. et al. Wattch: A framework for architectural-level power analysis and optimizations. In PROC. OF 27TH ANN. INT'L SYMP. COMPUTER ARCHITECTURE, pages 83-94. IEEE Computer Society Process, Los Alamitos, USA, 2000.
BURGER, D., AUSTIN, T. M.. The SimpleScalar Tool Set, Version 2.0. University of Wisconsin-Madison Computer Sciences Department. TR#1342, Jun. 1997.
FLAUTNER K., and MUDGE, T. Vertigo: automatic performance-setting for Linux. SIGOPS OPER. SYST. REV. 36, SI (DEC. 2002), 105-116.
GONÇALVES, R. A. L. et al. A Simulator for SMT Architecture: Evaluating Instruction Cache Topologies, SBAC-PAD, São Pedro, 2000.
GROHOSKI, G., Niagara-2: A Highly Threaded Serveron-a-Chip, in Hot Chips 2006.
HIRATA, H. et al. An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads. Proceedings of the 19th ISCA.
HOMAYOUN, H. et al. "Functional units power gating in SMT processors," Communications, Computers and signal Processing, 2005. PACRIM. 2005 IEEE Pacific Rim Conference on, vol., no., pp. 125-128, 24-26 Aug. 2005.
JOUPPI, N. and WILTON, S.. An enhanced access and cycle time model for on-chip caches. Technical Report TR-93-5, Compaq WRL, July 1994.
KALLA, R. et al. "IBM Power5 chip: a dual-core multithreaded processor," Micro, IEEE, vol.24, no.2, pp. 40-47, Mar-Apr 2004.
KONGETIRA, P. et al. "Niagara: a 32-way multithreaded Sparc processor," Micro, IEEE, vol.25, no.2, pp. 21-29, March-April 2005.
MCNAIRY, C.; BHATIA, R., "Montecito: a dual-core, dual-thread Itanium processor," Micro, IEEE, vol.25, no.2, pp. 10-20, March-April 2005.
MARUYAMA, T., “SPARC64 VI: Fujitsu’s Next Generation Processor,” in Microprocessor Forum, 2003.
MAMIDIPAKA, M., DUTT, N. eCACTI: An Enhanced Power Estimation Model for On-chip Caches. University of California Irvine Center for Embedded Computer Systems Technical Report TR-04-28, Sept. 2004.
MARR, D. T. et al. Hyper-Threading Technology Architecture and Microarchitecture. Intel Technology Journal, 6(1), February 2002.
OLUKOTUN, K. et al. The case for a single-chip multiprocessor. SIGPLAN N. 31, 9, 2-11, Sep. 1996.
REINMAN, G., and JOUPPI, N.. "CACTI 2.0: An integrated cache timing and power model," WRL Research Report 2000/7, Feb.2000.
SHIVAKUMAR, P. e JOUPPI, N. P.. CACTI 3.0: An Integrated Cache Timing, Power, and Area Model., TR Compaq Computer Corporation August, 2001.
SPRACKLEN, L.; ABRAHAM, S.G., "Chip multithreading: opportunities and challenges," High-Performance Computer Architecture, HPCA, Feb. 2005.
TARJAN, D. et al. CACTI 4.0, HP Laboratories Palo Alto, HPL-2006-86, June 2, 2006.
TULLSEN, D. M. et al. Simultaneous Multithreading: Maximizing On-Chip Parallelism, ISCA, Italy. 1995.
YAMAMOTO, W.; NEMIROVSKY, M. Performance Estimation of Multistreamed, Superscalar Processors, Proceedings of the Hawaii International Conference on System Sciences, January, 1994.
MANNE, S. et al. Pipeline gating: Speculation control for energy reduction. ISCA, Barcelona, 1998.
PARIKH, D. et al. Power issues related to branch prediction. Proceedings of the 8th International Symposium on High-Performance Computer Architecture, Feb. 2002.
ZHANG, Y. et al. HotLeakage: A temperatureaware model of subthreshold and gate leakage for architects. TRCS-2003-05, University of Virginia, Dept of Computer Science, March 2003.
YE, W. et al. The Design and Use of SimplePower: A cycle-accurate energy estimation tool. Proceedings of the Design Automation Conference, June 2000.
BROOKS, D. et al. Microarchitectural-Level Power-Performance Analysis: The PowerTimer Approach. IBM Journal of Research and Development, V.47, Nov. 2003.
LAURENT, J. et al. Functional level power analysis: an efficient approach for modeling the power consumption of complex processors. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, Feb. 2004.
MINHOLI, Diego H. et al. Correlacionando Desempenho e Potência em Processadores Superescalares: Analisando Cache e Janela de Instruções In: II Encontro Paranaense de Computação, Cascavel. Unioeste, Ago. 2007.
BURGER, D., AUSTIN, T. M.. The SimpleScalar Tool Set, Version 2.0. University of Wisconsin-Madison Computer Sciences Department. TR#1342, Jun. 1997.
FLAUTNER K., and MUDGE, T. Vertigo: automatic performance-setting for Linux. SIGOPS OPER. SYST. REV. 36, SI (DEC. 2002), 105-116.
GONÇALVES, R. A. L. et al. A Simulator for SMT Architecture: Evaluating Instruction Cache Topologies, SBAC-PAD, São Pedro, 2000.
GROHOSKI, G., Niagara-2: A Highly Threaded Serveron-a-Chip, in Hot Chips 2006.
HIRATA, H. et al. An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads. Proceedings of the 19th ISCA.
HOMAYOUN, H. et al. "Functional units power gating in SMT processors," Communications, Computers and signal Processing, 2005. PACRIM. 2005 IEEE Pacific Rim Conference on, vol., no., pp. 125-128, 24-26 Aug. 2005.
JOUPPI, N. and WILTON, S.. An enhanced access and cycle time model for on-chip caches. Technical Report TR-93-5, Compaq WRL, July 1994.
KALLA, R. et al. "IBM Power5 chip: a dual-core multithreaded processor," Micro, IEEE, vol.24, no.2, pp. 40-47, Mar-Apr 2004.
KONGETIRA, P. et al. "Niagara: a 32-way multithreaded Sparc processor," Micro, IEEE, vol.25, no.2, pp. 21-29, March-April 2005.
MCNAIRY, C.; BHATIA, R., "Montecito: a dual-core, dual-thread Itanium processor," Micro, IEEE, vol.25, no.2, pp. 10-20, March-April 2005.
MARUYAMA, T., “SPARC64 VI: Fujitsu’s Next Generation Processor,” in Microprocessor Forum, 2003.
MAMIDIPAKA, M., DUTT, N. eCACTI: An Enhanced Power Estimation Model for On-chip Caches. University of California Irvine Center for Embedded Computer Systems Technical Report TR-04-28, Sept. 2004.
MARR, D. T. et al. Hyper-Threading Technology Architecture and Microarchitecture. Intel Technology Journal, 6(1), February 2002.
OLUKOTUN, K. et al. The case for a single-chip multiprocessor. SIGPLAN N. 31, 9, 2-11, Sep. 1996.
REINMAN, G., and JOUPPI, N.. "CACTI 2.0: An integrated cache timing and power model," WRL Research Report 2000/7, Feb.2000.
SHIVAKUMAR, P. e JOUPPI, N. P.. CACTI 3.0: An Integrated Cache Timing, Power, and Area Model., TR Compaq Computer Corporation August, 2001.
SPRACKLEN, L.; ABRAHAM, S.G., "Chip multithreading: opportunities and challenges," High-Performance Computer Architecture, HPCA, Feb. 2005.
TARJAN, D. et al. CACTI 4.0, HP Laboratories Palo Alto, HPL-2006-86, June 2, 2006.
TULLSEN, D. M. et al. Simultaneous Multithreading: Maximizing On-Chip Parallelism, ISCA, Italy. 1995.
YAMAMOTO, W.; NEMIROVSKY, M. Performance Estimation of Multistreamed, Superscalar Processors, Proceedings of the Hawaii International Conference on System Sciences, January, 1994.
MANNE, S. et al. Pipeline gating: Speculation control for energy reduction. ISCA, Barcelona, 1998.
PARIKH, D. et al. Power issues related to branch prediction. Proceedings of the 8th International Symposium on High-Performance Computer Architecture, Feb. 2002.
ZHANG, Y. et al. HotLeakage: A temperatureaware model of subthreshold and gate leakage for architects. TRCS-2003-05, University of Virginia, Dept of Computer Science, March 2003.
YE, W. et al. The Design and Use of SimplePower: A cycle-accurate energy estimation tool. Proceedings of the Design Automation Conference, June 2000.
BROOKS, D. et al. Microarchitectural-Level Power-Performance Analysis: The PowerTimer Approach. IBM Journal of Research and Development, V.47, Nov. 2003.
LAURENT, J. et al. Functional level power analysis: an efficient approach for modeling the power consumption of complex processors. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, Feb. 2004.
MINHOLI, Diego H. et al. Correlacionando Desempenho e Potência em Processadores Superescalares: Analisando Cache e Janela de Instruções In: II Encontro Paranaense de Computação, Cascavel. Unioeste, Ago. 2007.
Publicado
29/10/2008
Como Citar
GONÇALVES, Rogério Aparecido; GONÇALVES, Ronaldo Augusto de Lara.
PowerSMT: Ferramenta para Análise de Consumo de Potência em Arquiteturas SMT. In: SIMPÓSIO EM SISTEMAS COMPUTACIONAIS DE ALTO DESEMPENHO (SSCAD), 9. , 2008, Campo Grande.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
2008
.
p. 177-184.
DOI: https://doi.org/10.5753/wscad.2008.17682.
