DONUTS: Um Eficiente Método de Checkpointing em Memórias Não Voláteis
Resumo
Os sistemas com memória não volátil (NVM) precisam ser consistentes à falhas. Dentre os principais desafios está criar mecanismos de checkpointing viáveis em termos de desempenho e usabilidade, para isso é necessário reduzir o número de escritas na NVM, pois o aumento excessivo gera maior uso de largura de banda e, consequentemente, degrada o desempenho. Neste trabalho é proposto DONUTS, um mecanismo transparente ao software que gera épocas dinâmicas por meio de checkpoints integrados à política de substituição de cache. Comparado ao sistema anterior de melhor desempenho, o método proposto reduziu a quantidade de escritas na NVM em 53,8%, fornecendo consistência à falhas com menos de 1% de overhead de tempo de execução.
Referências
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Noguchi, H., Ikegami, K., Kushida, K., Abe, K., Itai, S., Takaya, S., Shimomura, N., Ito, J., Kawasumi, A., Hara, H., and Fujita, S. (2015). 7.5 a 3.3ns-access-time 71.2µw/mhz 1mb embedded stt-mram using physically eliminated read-disturb scheme and normally-off memory architecture. In 2015 IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, pages 1–3.
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Wei, X., Feng, D., Tong, W., Liu, J., Wang, C., and Ye, L. (2020). Cchl: Compressionconsolidation hardware logging for efficient failure-atomic persistent memory updates. In 49th International Conference on Parallel Processing ICPP, ICPP ’20, New York, NY, USA. Association for Computing Machinery.
Wei, X., Feng, D., Tong, W., LIU, J., and Ye, L. (2019). Nico: Reducing software transparent crash consistency cost for persistent memory. IEEE Transactions on Computers, 68(9):1313–1324.
Wu, Q., Sun, F., Xu, W., and Zhang, T. (2013). Using multilevel phase change memory to build data storage: A time-aware system design perspective. IEEE Transactions on Computers, 62(10):2083–2095.
Wu, S., Zhou, F., Gao, X., Jin, H., and Ren, J. (2019). Dual-page checkpointing: An architectural approach to efficient data persistence for in-memory applications. ACM Trans. Archit. Code Optim., 15(4).
Chakrabarti, D. R., Boehm, H.-J., and Bhandari, K. (2014). Atlas: Leveraging locks for non-volatile memory consistency. SIGPLAN Not., 49(10):433–452.
Coburn, J., Caulfield, A. M., Akel, A., Grupp, L. M., Gupta, R. K., Jhala, R., and Swanson, S. (2011). Nv-heaps: Making persistent objects fast and safe with next-generation, non-volatile memories. SIGARCH Comput. Archit. News, 39(1):105–118.
Doshi, K., Giles, E., and Varman, P. (2016). Atomic persistence for scm with a non-intrusive backend controller. volume 2016-April, pages 77–89.
Fackenthal, R., Kitagawa, M., Otsuka, W., Prall, K., Mills, D., Tsutsui, K., Javanifard, J., Tedrow, K., Tsushima, T., Shibahara, Y., and Hush, G. (2014). 19.7 a 16gb reram with 200mb/s write and 1gb/s read in 27nm technology. In 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pages 338–339.
Giles, E., Doshi, K., and Varman, P. (2015). Softwrap: A lightweight framework for transactional support of storage class memory. volume 2015-August.
Gogte, V., Diestelhorst, S., Wang, W., Narayanasamy, S., Chen, P. M., and Wenisch, T. F. (2018). Persistency for synchronization-free regions. SIGPLAN Not., 53(4):46–61.
Hsu, T. C.-H., Brügner, H., Roy, I., Keeton, K., and Eugster, P. (2017). Nvthreads: Practical persistence for multi-threaded applications. In Proceedings of the Twelfth European Conference on Computer Systems, EuroSys ’17, page 468–482, New York, NY, USA. Association for Computing Machinery.
Intel (2015). Intel and micron produce breakthrough memory technology.
Jeong, J., Park, C., Huh, J., and Maeng, S. (2018). Efficient hardware-assisted logging with asynchronous and direct-update for persistent memory. volume 2018-October, pages 520–532.
Joshi, A., Nagarajan, V., Viglas, S., and Cintra, M. (2017). Atom: Atomic durability in non-volatile memory through hardware logging. In 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA), pages 361–372.
Kolli, A., Pelley, S., Saidi, A., Chen, P., and Wenisch, T. (2016). High-performance transactions for persistent memories. volume 02-06-April-2016, pages 399–411.
Liu, M., Zhang, M., Chen, K., Qian, X., Wu, Y., Zheng, W., and Ren, J. (2017). Dudetm: Building durable transactions with decoupling for persistent memory. volume Part F127193, pages 329–343.
Nguyen, T. M. and Wentzlaff, D. (2018). Picl: A software-transparent, persistent cache log for nonvolatile main memory. In 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pages 507–519.
Ni, Y., Zhao, J., Litz, H., Bittman, D., and Miller, E. (2019). Ssp: Eliminating redundant writes in failure-atomic nvrams via shadow sub-paging. pages 836–848.
Noguchi, H., Ikegami, K., Kushida, K., Abe, K., Itai, S., Takaya, S., Shimomura, N., Ito, J., Kawasumi, A., Hara, H., and Fujita, S. (2015). 7.5 a 3.3ns-access-time 71.2µw/mhz 1mb embedded stt-mram using physically eliminated read-disturb scheme and normally-off memory architecture. In 2015 IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, pages 1–3.
Ogleari, M., Miller, E., and Zhao, J. (2018). Steal but no force: Efficient hardware undo+redo logging for persistent memory systems. volume 2018-February, pages 336– 349.
Ren, J., Zhao, J., Khan, S., Choi, J., Wu, Y., and Mutiu, O. (2015). Thynvm: Enabling In 2015 48th software-transparent crash consistency in persistent memory systems. Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pages 672–685.
Shin, S., Tirukkovalluri, S. K., Tuck, J., and Solihin, Y. (2017). Proteus: A flexible and In 2017 50th Annual fast software supported hardware logging approach for nvm. IEEE/ACM International Symposium on Microarchitecture (MICRO), pages 178–190.
Volos, H., Tack, A., and Swift, M. (2011). Mnemosyne: Lightweight persistent memory. pages 91–103.
Wei, X., Feng, D., Tong, W., Liu, J., Wang, C., and Ye, L. (2020). Cchl: Compressionconsolidation hardware logging for efficient failure-atomic persistent memory updates. In 49th International Conference on Parallel Processing ICPP, ICPP ’20, New York, NY, USA. Association for Computing Machinery.
Wei, X., Feng, D., Tong, W., LIU, J., and Ye, L. (2019). Nico: Reducing software transparent crash consistency cost for persistent memory. IEEE Transactions on Computers, 68(9):1313–1324.
Wu, Q., Sun, F., Xu, W., and Zhang, T. (2013). Using multilevel phase change memory to build data storage: A time-aware system design perspective. IEEE Transactions on Computers, 62(10):2083–2095.
Wu, S., Zhou, F., Gao, X., Jin, H., and Ren, J. (2019). Dual-page checkpointing: An architectural approach to efficient data persistence for in-memory applications. ACM Trans. Archit. Code Optim., 15(4).
Publicado
26/10/2021
Como Citar
KRUGER, Kleber; AZEVEDO, Rodolfo; PANNAIN, Ricardo.
DONUTS: Um Eficiente Método de Checkpointing em Memórias Não Voláteis. In: SIMPÓSIO EM SISTEMAS COMPUTACIONAIS DE ALTO DESEMPENHO (SSCAD), 22. , 2021, Belo Horizonte.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
2021
.
p. 120-131.
DOI: https://doi.org/10.5753/wscad.2021.18517.
