Arquitetura de Cache com Associatividade Reconfigurável
Resumo
Neste artigo apresentamos uma arquitetura de cache com associatividade reconfigurável. Nossos objetivos principais são: propor e analisar uma arquitetura de memória cache com associatividade reconfigurável/variável. Apresentamos a taxa de erro da execução de algumas cargas de trabalho reais representadas por traces obtidos do BYU Trace Distribution Center. Analisamos o desempenho da arquitetura proposta através de comparação das taxas de erro obtidas através da simulação da arquitetura e de caches associativas por conjunto. Além disso, analisamos o espaço necessário para armazenar as tags na cache. Nossa principal contribuição é a proposta de uma arquitetura de memória cache com associatividade reconfigurável/variável capaz de se adaptar às diferentes cargas de trabalho.
Referências
D. H, Albonesi. Et ai. Dynamically tuning processor resources with adaptive processing. IEEE Computer, 12(36):49-58, 2003.
B. Batson, T. N. Vijaykumar. Reactive-associative caches, Proceedings of IEEE International Conference on Parallel Architectures and Compilation Techniques, pages 49-60, September 2001.
A. W. Burks, H. H. Goldstine, J. von Neuman. Preliminary discussion of the logical design of an electronic computing instrument Disponível em: http://www.cs.unc.edu/~adyilie/comp265/vonNeumann.html
K. Compton, S. Hauck. Reconfigurable Computing: A Survey of Systems and Software, ACM Computing Survey, 34(2): 171-210, 2002.
J.K. Flanagan, B. Nelson, J. Archibald, K. Grimsrud. BACH: BYU Address Collection Hardware, the Collection of Complete Traces, Proceedings of the 6th International Conference on Modeling Techniques and Tools for Computer Performance Evaluation, Edinburgh U.K., September 1992, pp. 128-137.
L. F. W. Góes, C. A. P. S Martins. ClusterSim: A Java Parallel Discrete Event Simulation Tool, IEEE International Conference on Cluster Computing, 2004. (a ser publicado)
J. L. Hennessy and D. A. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufman, 3th Edition, 2003.
J.L. Henning. SPEC CPU2000: Measuring CPU Performance in the New Millennium, IEEE Computer, v.33, n.7, July 2000, pp. 28-35.
K. Inoue, T. Ishihara, K. Murakami. Way-predicting set-associative cache for high performance and low energy consumption, Proceedings of the ACM 1999 international symposium on Low power electronics and design, pages 273-275, August 1999.
R. K. Jain. The Arl of Computer Systems Performance Analysis: Techniques for Experimental Design, Measurement, Simulation and Modeling, John Wiley & Sons, 1991.
T. L. Johnson, D. A. Connors and W. W. Hwu. Runtime adaptive cache management, Proceedings of the Thirty-First Hawaii International Conference on System Sciences, 7(6-9): 774-775, January 1998.
C. Martins, E. Ordonez, J. Corrêa and M. Carvalho. Reconfigurable Computing: concepts, tendencies and application. In: XXII Jornada de Atualização em Informática (JAI), SBC2003, Vol. 2, 2003, p.339- 388. (In Portuguese)
M. D. Powell, A. Agarwall, T. N. Vijaykumar, B. Falsafi and K. Roy. Reducing set-associative cache energy via way-prediction and selective direct-mapping, Proceedings of 34th ACM/IEEE International Symposium on Microarchitecture, pp. 54-65, December 2001.
A. J. Smith. Cache Memories, ACM Computing Surveys, 14(3):473-530, September 1982.
W. Tang, A. Veidenbaum, A. Nicolau and R. Gupta. Cache With Adaptive Fetch Size, Technical Report ICS-00-16 of University of California, Irvine, April 2000.
R. A. Uhlig, T. N. Mudge. Trace-driven memory simulation: a survey, ACM Computing Surveys, 29(2): 128-170, June 1997.
A. Veidenbaum, W. Tang, R. Gupta, A. Nicolau, X. Ji. Adapting Cache Line Size to Application Behavior, Proceedings of the 13th ACM International Conference on Supercomputing, pp. 145-154, Rhodes, 1999.
Brigham Young University Trace Distribution Website: http://traces.byu.edu/
Laboratório de Sistemas Digitais e Computacionais (LSDC) Website: http://www.ppgee.pucminas.br/lsdc/
SPEC - Standard Performance Evaluation Corporation Website: http://www.spec.org/
B. Batson, T. N. Vijaykumar. Reactive-associative caches, Proceedings of IEEE International Conference on Parallel Architectures and Compilation Techniques, pages 49-60, September 2001.
A. W. Burks, H. H. Goldstine, J. von Neuman. Preliminary discussion of the logical design of an electronic computing instrument Disponível em: http://www.cs.unc.edu/~adyilie/comp265/vonNeumann.html
K. Compton, S. Hauck. Reconfigurable Computing: A Survey of Systems and Software, ACM Computing Survey, 34(2): 171-210, 2002.
J.K. Flanagan, B. Nelson, J. Archibald, K. Grimsrud. BACH: BYU Address Collection Hardware, the Collection of Complete Traces, Proceedings of the 6th International Conference on Modeling Techniques and Tools for Computer Performance Evaluation, Edinburgh U.K., September 1992, pp. 128-137.
L. F. W. Góes, C. A. P. S Martins. ClusterSim: A Java Parallel Discrete Event Simulation Tool, IEEE International Conference on Cluster Computing, 2004. (a ser publicado)
J. L. Hennessy and D. A. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufman, 3th Edition, 2003.
J.L. Henning. SPEC CPU2000: Measuring CPU Performance in the New Millennium, IEEE Computer, v.33, n.7, July 2000, pp. 28-35.
K. Inoue, T. Ishihara, K. Murakami. Way-predicting set-associative cache for high performance and low energy consumption, Proceedings of the ACM 1999 international symposium on Low power electronics and design, pages 273-275, August 1999.
R. K. Jain. The Arl of Computer Systems Performance Analysis: Techniques for Experimental Design, Measurement, Simulation and Modeling, John Wiley & Sons, 1991.
T. L. Johnson, D. A. Connors and W. W. Hwu. Runtime adaptive cache management, Proceedings of the Thirty-First Hawaii International Conference on System Sciences, 7(6-9): 774-775, January 1998.
C. Martins, E. Ordonez, J. Corrêa and M. Carvalho. Reconfigurable Computing: concepts, tendencies and application. In: XXII Jornada de Atualização em Informática (JAI), SBC2003, Vol. 2, 2003, p.339- 388. (In Portuguese)
M. D. Powell, A. Agarwall, T. N. Vijaykumar, B. Falsafi and K. Roy. Reducing set-associative cache energy via way-prediction and selective direct-mapping, Proceedings of 34th ACM/IEEE International Symposium on Microarchitecture, pp. 54-65, December 2001.
A. J. Smith. Cache Memories, ACM Computing Surveys, 14(3):473-530, September 1982.
W. Tang, A. Veidenbaum, A. Nicolau and R. Gupta. Cache With Adaptive Fetch Size, Technical Report ICS-00-16 of University of California, Irvine, April 2000.
R. A. Uhlig, T. N. Mudge. Trace-driven memory simulation: a survey, ACM Computing Surveys, 29(2): 128-170, June 1997.
A. Veidenbaum, W. Tang, R. Gupta, A. Nicolau, X. Ji. Adapting Cache Line Size to Application Behavior, Proceedings of the 13th ACM International Conference on Supercomputing, pp. 145-154, Rhodes, 1999.
Brigham Young University Trace Distribution Website: http://traces.byu.edu/
Laboratório de Sistemas Digitais e Computacionais (LSDC) Website: http://www.ppgee.pucminas.br/lsdc/
SPEC - Standard Performance Evaluation Corporation Website: http://www.spec.org/
Publicado
27/10/2004
Como Citar
CARVALHO, Milene B.; MARTINS, Carlos A. P. S..
Arquitetura de Cache com Associatividade Reconfigurável. In: SIMPÓSIO EM SISTEMAS COMPUTACIONAIS DE ALTO DESEMPENHO (SSCAD), 5. , 2004, Foz do Iguaçu.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
2004
.
p. 50-57.
DOI: https://doi.org/10.5753/wscad.2004.19000.
